Dev-param

qspi.clk_src

Specify the clock source. The value corresponds to what is mentioned in the QSPI CLK SRC register.

0: pllp_out0

4: pllc4_muxed

devinfo.qspi.clk_src = 0; #

qspi.clk_div

clk_div = N+1;Hence N = 3 & clk_rate = 163.2 MHz = (408 MHz / ((N / 2) + 1))

devinfo.qspi.clk_div = 4;

qspi.width

Specify the width of the QSPI BUS during transfer

0 : 1 bit (x1 mode)

1 : 2 bit (x2 mode)

2 : 4 bit (x4 mode)

devinfo.qspi.width = 2

qspi.dma_type

Specify which DMA to use for transfer if mode of transfer is DMA. For QSPI, in MB1/MB2, BPMP-DMA should be used.

0 : GPC-DMA

1 : BPMP-DMA

devinfo.qspi.dma_type = 1

qspi.xfer_mode

Specify mode of transfer 0: PIO

1: DMA

devinfo.qspi.xfer_mode = 1;

qspi.read_dummy_cycles

The dummy cycles allow the device internal circuits additional time for accessing the initial address location. During the dummy cycles the data value on IOs are  "don't care" and may be high impedance.

devinfo.qspi.read_dummy_cycles = 9

qspi.trimmer_val1

tx_clk_tap_delay for QSPI

devinfo.qspi.trimmer_val1 = 0

qspi.trimmer_val2

rx_clk_tap_delay for QSPI

devinfo.qspi.trimmer_val2 = 0