PCIe#

Bringing Up PCIe Controllers in Root Port or Endpoint Modes#

To enable a PCIe controller in either Root Port (RP) or Endpoint (EP) mode, use the appropriate bind partition flags. Refer to ${NV_WORKSPACE}/platform-config/hardware/nvidia/platform/t264/automotive/pct/drive_av/${VM}/common_profile.mk for default platform settings, where {VM} is linux for Linux VPM and qnx for QNX VM.

Bind Partition Flags:

Root Port mode:

  • ENABLE_T264_PCIE_C0: C0 PCIe controller (dedicated for iGPU)

  • ENABLE_T264_PCIE_C1: C1 PCIe controller

  • ENABLE_T264_PCIE_C2: C2 PCIe controller

  • ENABLE_T264_PCIE_C3: C3 PCIe controller

  • ENABLE_T264_PCIE_C4: C4 PCIe controller

  • ENABLE_T264_PCIE_C5: C5 PCIe controller

Endpoint mode:

  • ENABLE_T264_PCIE_C2_EP: C2 PCIe controller

  • ENABLE_T264_PCIE_C4_EP: C4 PCIe controller

  • ENABLE_T264_PCIE_C5_EP: C5 PCIe controller

Enabling a bind partition flag performs the following actions:

  • Enables the PCIe device tree node in the BPMP-FW device tree with pcie-mode set to RP (Root Port, value 1) or EP (Endpoint, value 2). Available device tree nodes are:

    • For RP mode (pcie-mode = 1): pcie@0, pcie@1, pcie@2, pcie@3, pcie@4, pcie@5

    • For EP mode (pcie-mode = 2): pcie@2, pcie@4, pcie@5

  • Enables the PCIe controller Linux device tree node. Available Linux kernel device tree nodes are:

    • For RP mode: - pcie@d0b0000000 (C0) - pcie@a8b0000000 (C1) - pcie@b0b0000000 (C2) - pcie@b8b0000000 (C3) - pcie@c0b0000000 (C4) - pcie@c8b0000000 (C5)

    • For EP mode: - pcie-ep@a808420000 (C2) - pcie-ep@a808460000 (C4) - pcie-ep@a808480000 (C5)

  • Assigns PCIe controller ownership to the PCIe IOV server (RP mode) or Guest VM (EP mode). For details, refer to ${NV_WORKSPACE}/platform-config/hardware/nvidia/platform/t264/automotive/pct/drive_av/${VM}/guest_io_periph_assign.h, where {VM} is linux for Linux VPM and qnx for QNX VM.

PCIe Clock Scheme Configuration#

On Thor (T264) silicon, the PCIe controller supports three clock schemes:

  • Common Clock: The reference clock is shared between the Root Complex and Endpoint.

  • SRNS (Separate Reference No Spread): Separate reference clocks with no spread-spectrum clocking.

  • SRIS (Separate Reference Independent Spread): Separate reference clocks with independent spread-spectrum clocking.

Clock schemes are configured in the BPMP-FW device tree under the respective PCIe controller node (pcie@1 through pcie@5). For the location of BPMP-FW device tree source files and instructions on modifying and compiling them, refer to Modifying and Compiling the BPMP-FW Device Tree.

Default Settings#

The default MB1 settings enable spread with 5000 PPM. Refer to ${NV_WORKSPACE}/platform-config/hardware/nvidia/platform/t264/common/bct/mb1bct/clock_data/tegra264-mb1-bct-boot-clocks-defaults.dtsi for the default clock configuration.

Constraints for SRIS and SRNS Clock Modes#

Each PCIe controller on the Thor SoC can independently use Common Clock alongside either SRIS or SRNS. However, SRIS and SRNS cannot be mixed across controllers within the same SoC. This is because the PLLE clock is shared across all PCIe controllers.

In other words, a platform can choose one of the following configurations:

  • Common Clock + SRIS: Any controller can use Common Clock or SRIS.

  • Common Clock + SRNS: Any controller can use Common Clock or SRNS.

The following table shows the allowed combinations:

Allowed Clock Mode Combinations Across PCIe Controllers#

Platform Clock Policy

Common Clock

SRIS

SRNS

Common Clock + SRIS

Yes

Yes

No

Common Clock + SRNS

Yes

No

Yes

For example, if PCIe C1 uses SRNS, then PCIe C2 through C5 must use SRNS or Common Clock, and none of them can use SRIS. Likewise, when a platform uses Common Clock + SRIS, no controller can use SRNS.

SRIS Configuration#

When SRIS is used with Gen 5, a PPM override to 3000 is required. For the P3960 platform, this override is applied to the C4 and C5 controllers used for chip-to-chip (C2C) communication.

SRNS Configuration#

If a platform uses SRNS for a controller, the enable_ss property of plle@0 must be set to 0. A BCT override to disable spread must be added. Refer to ${NV_WORKSPACE}/platform-config/hardware/nvidia/platform/t264/automotive/automotive-platform-configs/driveos_customer_config/nv_platforms/p3960/p3960-10/common/bct/misc/tegra264-mb1-bct-misc-p3960-0010.dts for a reference configuration.

Warning

Disabling spread for PLLE0 impacts USB3 certification. Platform designs requiring USB3 certification must account for this trade-off.

Note

Hardware EMI considerations related to SRNS mode must be addressed by platform hardware designers.