UART IO Tuning#

Note

This section provides examples of using DriveOS software to tune UART registers. For the actual tuning procedure, contact your NVIDIA representative for the UART I/O Tuning Guide.

Tune the UART interface by configuring the UART PADCTL registers in the MB1 Boot Configuration Table (BCT).

BCT is used to configure the UART PADCTL registers with the desired values.

Find the right register values faster by using runtime register access available in dev_nsr builds. For more information, see Method 1: Read/Write Access for Tuning Registers.

Customer Modifiable UART PADCTL Registers in Thor#

Register Name

Address (64-bit)

Address (32-bit)

Tunable Fields (Bit Range)

PADCTL_SYS_AO_2_CFG2TMC_UART0_TX_0

0x0c7a302c

0x8c7a302c

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

PADCTL_SYS_AO_2_CFG2TMC_UART0_RX_0

0x0c7a3034

0x8c7a3034

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

PADCTL_G4_CFG2TMC_UART4_TX_0

0x810c2870cc

0xac2870cc

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

PADCTL_G4_CFG2TMC_UART4_RX_0

0x810c2870c4

0xac2870c4

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

PADCTL_G4_CFG2TMC_UART4_RTS_N_0

0x810c2870bc

0xac2870bc

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

PADCTL_G4_CFG2TMC_UART4_CTS_N_0

0x810c2870b4

0xac2870b4

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

PADCTL_G2_CFG2TMC_UART5_TX_0

0x810c281074

0xac281074

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

PADCTL_G2_CFG2TMC_UART5_RX_0

0x810c28106c

0xac28106c

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

PADCTL_G2_CFG2TMC_UART5_RTS_N_0

0x810c281064

0xac281064

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

PADCTL_G2_CFG2TMC_UART5_CTS_N_0

0x810c28105c

0xac28105c

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

PADCTL_G3_CFG2TMC_UART9_TX_0

0x810c28206c

0xac28206c

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

PADCTL_G3_CFG2TMC_UART9_RX_0

0x810c282064

0xac282064

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

PADCTL_G3_CFG2TMC_UART9_RTS_N_0

0x810c28205c

0xac28205c

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

PADCTL_G3_CFG2TMC_UART9_CTS_N_0

0x810c282054

0xac282054

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

PADCTL_G2_CFG2TMC_UART10_TX_0

0x810c28102c

0xac28102c

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

PADCTL_G2_CFG2TMC_UART10_RX_0

0x810c281024

0xac281024

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

PADCTL_G2_CFG2TMC_UART10_RTS_N_0

0x810c28101c

0xac28101c

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

PADCTL_G2_CFG2TMC_UART10_CTS_N_0

0x810c281014

0xac281014

CFG_CAL_DRVUP (23:20), CFG_CAL_DRVDN (15:12)

For additional information, refer to the register definition in the SoC Technical Reference Manual (TRM).

MB1 BCT Configuration#

For production deployment, configure UART PADCTL register values in the MB1 BCT configuration file using 32-bit addresses. This method works for all PCT variants.

Configuration File Location#

Edit the BCT configuration file located at:

${NV_WORKSPACE}/drive-foundation/platform-config/hardware/nvidia/platform/t264/automotive/automotive-platform-configs/driveos_customer_config/nv_platforms/<board>/<board>-<sku>/common/bct/prod/tegra264-mb1-bct-prod-<board>-<sku>.dts

Configuration Format#

UART PADCTL registers are configured using the following format:

<address mask value>, // Comment

Where:

  • address: 32-bit register address (from Address (32-bit) column in the register table)

  • mask: Bit mask for the fields to modify (0x00f0f000 for DRVUP and DRVDN fields)

  • value: Register value with desired DRVUP (bits 23:20) and DRVDN (bits 15:12) settings

The mask 0x00f0f000 covers:

  • Bits 23:20 (DRVUP): 0x00f00000

  • Bits 15:12 (DRVDN): 0x0000f000

Example Configuration for UART10#

<0xac281014 0x00f0f000 0x00808000>, // PADCTL_G2_CFG2TMC_UART10_CTS_N_0: DRVUP=0x8, DRVDN=0x8
<0xac28101c 0x00f0f000 0x00808000>, // PADCTL_G2_CFG2TMC_UART10_RTS_N_0: DRVUP=0x8, DRVDN=0x8
<0xac281024 0x00f0f000 0x00808000>, // PADCTL_G2_CFG2TMC_UART10_RX_0:    DRVUP=0x8, DRVDN=0x8
<0xac28102c 0x00f0f000 0x00808000>, // PADCTL_G2_CFG2TMC_UART10_TX_0:    DRVUP=0x8, DRVDN=0x8

Example Configuration for UART4#

<0xac2870b4 0x00f0f000 0x00a05000>, // PADCTL_G4_CFG2TMC_UART4_CTS_N_0: DRVUP=0xA, DRVDN=0x5
<0xac2870bc 0x00f0f000 0x00b06000>, // PADCTL_G4_CFG2TMC_UART4_RTS_N_0: DRVUP=0xB, DRVDN=0x6
<0xac2870c4 0x00f0f000 0x00c07000>, // PADCTL_G4_CFG2TMC_UART4_RX_0:    DRVUP=0xC, DRVDN=0x7
<0xac2870cc 0x00f0f000 0x00d08000>, // PADCTL_G4_CFG2TMC_UART4_TX_0:    DRVUP=0xD, DRVDN=0x8

Calculating Register Values#

To calculate the value field:

  1. Choose DRVUP value (0x0 to 0xF)

  2. Choose DRVDN value (0x0 to 0xF)

  3. Calculate: value = (DRVUP << 20) | (DRVDN << 12)

Example calculations:

DRVUP

DRVDN

Value

Calculation

0x8

0x8

0x00808000

(0x8 << 20) | (0x8 << 12) = 0x00808000

0xA

0x5

0x00a05000

(0xA << 20) | (0x5 << 12) = 0x00a05000

0xF

0xF

0x00f0f000

(0xF << 20) | (0xF << 12) = 0x00f0f000

MB1 BCT Pinmux Configuration#

Alternatively, you can configure UART pin properties using the pinmux device tree format. This provides more control over individual pin properties beyond drive strength.

Configuration File Location#

Edit the BCT pinmux configuration file located at:

${NV_WORKSPACE}/drive-foundation/platform-config/hardware/nvidia/platform/t264/automotive/automotive-platform-configs/driveos_customer_config/nv_platforms/<board>/<sku>/common/bct/pinmux/tegra264-mb1-bct-pinmux-<board>-<sku>.dtsi

Configuration Format#

UART PADCTL pins are configured using device tree syntax with the following properties:

uart<X>_<signal>_<pin> {
    nvidia,pins = "uart<X>_<signal>_<pin>";
    nvidia,function = "<function_name>";
    nvidia,pull = <TEGRA_PIN_PULL_NONE | TEGRA_PIN_PULL_DOWN | TEGRA_PIN_PULL_UP>;
    nvidia,tristate = <TEGRA_PIN_DISABLE | TEGRA_PIN_ENABLE>;
    nvidia,enable-input = <TEGRA_PIN_DISABLE | TEGRA_PIN_ENABLE>;
    nvidia,drv-type = <TEGRA_PIN_1X_DRIVER | TEGRA_PIN_2X_DRIVER>;
    nvidia,e-io-od = <TEGRA_PIN_DISABLE | TEGRA_PIN_ENABLE>;
    nvidia,e-lpbk = <TEGRA_PIN_DISABLE | TEGRA_PIN_ENABLE>;
};

The macro definitions are available in:

${NV_WORKSPACE}/drive-foundation/platform-config/hardware/nvidia/tegra/nv-public/include/kernel/dt-bindings/pinctrl/pinctrl-tegra.h

Example Configuration for UART9 (UARTJ)#

uart9_tx_pm2 {
    nvidia,pins = "uart9_tx_pm2";
    nvidia,function = "uartj_txd";
    nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    nvidia,tristate = <TEGRA_PIN_DISABLE>;
    nvidia,enable-input = <TEGRA_PIN_DISABLE>;
    nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
    nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
    nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
};

uart9_rx_pm3 {
    nvidia,pins = "uart9_rx_pm3";
    nvidia,function = "uartj_rxd";
    nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    nvidia,tristate = <TEGRA_PIN_DISABLE>;
    nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
    nvidia,e-io-od = <TEGRA_PIN_DISABLE>;
    nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
};

Common Configuration Properties#

Property

Description

nvidia,pull

Pull-up/pull-down configuration: TEGRA_PIN_PULL_NONE, TEGRA_PIN_PULL_DOWN, TEGRA_PIN_PULL_UP

nvidia,tristate

Tristate control: TEGRA_PIN_DISABLE (normal operation), TEGRA_PIN_ENABLE (high-Z)

nvidia,enable-input

Input buffer control: TEGRA_PIN_ENABLE (input), TEGRA_PIN_DISABLE (output only)

nvidia,drv-type

Drive strength: TEGRA_PIN_1X_DRIVER (normal), TEGRA_PIN_2X_DRIVER (double strength)

nvidia,e-io-od

Open drain mode: TEGRA_PIN_DISABLE (push-pull), TEGRA_PIN_ENABLE (open drain)

nvidia,e-lpbk

Loopback mode: TEGRA_PIN_DISABLE (normal), TEGRA_PIN_ENABLE (loopback)

Building and Flashing#

After editing the BCT configuration file:

  1. The BCT is rebuilt automatically during bind_partitions.

  2. Create the image:

    ./make/bind_partitions [-b <board_name>] <pct> -p <pct_variant>

  3. Flash the platform normally using the bootburn procedure.

Note

Changes to the BCT configuration require reflashing the platform to take effect.