I2C IO Tuning#

Note

This section provides examples of using DriveOS software to tune I2C registers. For the actual tuning procedure, contact your NVIDIA representative for the I2C I/O Tuning Guide.

Tune the I2C interface by configuring the I2C PADCTL registers in the MB1 Boot Configuration Table (BCT).

BCT is used to configure the I2C PADCTL registers with the desired values.

Find the right register values faster by using runtime register access available in dev_nsr builds. For more information, see Method 1: Read/Write Access for Tuning Registers.

Customer Modifiable I2C PADCTL Registers in Thor#

Note

DP_AUX instances (I2C4, I2C6, I2C8, I2C10) can be used as I2C and are covered in this document.

Drive Strength Control Registers#

I2C Channel

Instance

Register Name

64-bit Address

32-bit Address

Tunable Fields

Gen0_I2C

I2C0

PADCTL_G4_CFG2TMC_GEN0_I2C_SCL_0

0x810c287004

0xac287004

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

PADCTL_G4_CFG2TMC_GEN0_I2C_SDA_0

0x810c28700c

0xac28700c

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

Gen1_I2C

I2C1

PADCTL_G4_CFG2TMC_GEN1_I2C_SCL_0

0x810c287014

0xac287014

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

PADCTL_G4_CFG2TMC_GEN1_I2C_SDA_0

0x810c28701c

0xac28701c

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

Gen2_I2C

I2C2

PADCTL_SYS_AO_2_CFG2TMC_GEN2_I2C_SCL_0

0x0c7a3004

0x8c7a3004

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

PADCTL_SYS_AO_2_CFG2TMC_GEN2_I2C_SDA_0

0x0c7a300c

0x8c7a300c

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

Gen3_I2C

I2C3

PADCTL_SYS_AO_2_CFG2TMC_GEN3_I2C_SCL_0

0x0c7a3014

0x8c7a3014

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

PADCTL_SYS_AO_2_CFG2TMC_GEN3_I2C_SDA_0

0x0c7a301c

0x8c7a301c

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

Gen4_I2C/DP_AUX

I2C4

PADCTL_EDP_CFG2TMC_DP_AUX_CH2_HPD_0

0x810c28802c

0xac28802c

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

Gen5_I2C/PWR_I2C

I2C5

PADCTL_G4_CFG2TMC_PWR_I2C_SCL_0

0x810c2870dc

0xac2870dc

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

PADCTL_G4_CFG2TMC_PWR_I2C_SDA_0

0x810c2870d4

0xac2870d4

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

Gen6_I2C/DP_AUX

I2C6

PADCTL_EDP_CFG2TMC_DP_AUX_CH0_HPD_0

0x810c28801c

0xac28801c

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

Gen7_I2C

I2C7

PADCTL_EDP_CFG2TMC_GEN7_I2C_SCL_0

0x810c28804c

0xac28804c

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

PADCTL_EDP_CFG2TMC_GEN7_I2C_SDA_0

0x810c288054

0xac288054

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

Gen8_I2C/DP_AUX

I2C8

PADCTL_EDP_CFG2TMC_DP_AUX_CH3_HPD_0

0x810c288034

0xac288034

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

Gen9_I2C

I2C9

PADCTL_EDP_CFG2TMC_GEN9_I2C_SCL_0

0x810c28805c

0xac28805c

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

PADCTL_EDP_CFG2TMC_GEN9_I2C_SDA_0

0x810c288064

0xac288064

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

Gen10_I2C/DP_AUX

I2C10

PADCTL_EDP_CFG2TMC_DP_AUX_CH1_HPD_0

0x810c288024

0xac288024

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

Gen11_I2C

I2C11

PADCTL_G5_CFG2TMC_GEN11_I2C_SCL_0

0x810c2860b4

0xac2860b4

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

PADCTL_G5_CFG2TMC_GEN11_I2C_SDA_0

0x810c2860bc

0xac2860bc

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

Gen12_I2C

I2C12

PADCTL_G2_CFG2TMC_GEN12_I2C_SCL_0

0x810c2810b4

0xac2810b4

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

PADCTL_G2_CFG2TMC_GEN12_I2C_SDA_0

0x810c2810bc

0xac2810bc

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

Gen13_I2C

I2C13

PADCTL_FSI_G5_CFG2TMC_GEN13_I2C_SCL_0

0x811031400c

0xb031400c

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

PADCTL_FSI_G5_CFG2TMC_GEN13_I2C_SDA_0

0x8110314004

0xb0314004

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

Gen14_I2C

I2C14

PADCTL_G5_CFG2TMC_SOC_GPIO138_0

0x810c286004

0xac286004

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

PADCTL_G5_CFG2TMC_SOC_GPIO139_0

0x810c28600c

0xac28600c

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

Gen15_I2C

I2C15

PADCTL_G3_CFG2TMC_SOC_GPIO129_0

0x810c28202c

0xac28202c

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

PADCTL_G3_CFG2TMC_SOC_GPIO130_0

0x810c282034

0xac282034

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

Gen16_I2C

I2C16

PADCTL_G8_CFG2TMC_SOC_GPIO270_0

0x810c28b004

0xac28b004

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

PADCTL_G8_CFG2TMC_SOC_GPIO271_0

0x810c28b00c

0xac28b00c

CFG_CAL_DRVUP [23:20], CFG_CAL_DRVDN [15:12]

For additional information, refer to the register definition in the SoC Technical Reference Manual (TRM).

Drive Type Setting Registers#

In addition to drive strength control (CFG_CAL_DRVUP/CFG_CAL_DRVDN), I2C pins support drive type settings to adjust the driver strength. The DRV_TYPE field can be configured to use either 1x driver (default) or 2x driver mode.

Note

DRV_TYPE setting can be used to narrow the gap or meet SCL rise and fall time minimum specification limits, or SDA fall time minimum specification limits. By default, DRV_TYPE is set to 0x0 (1x driver) for all I2C bus instances.

I2C Channel

Instance

Register Name

64-bit Address

32-bit Address

Tunable Fields

Gen0_I2C

I2C0

PADCTL_G4_GEN0_I2C_SCL_0

0x810c287000

0xac287000

DRV_TYPE [8]

PADCTL_G4_GEN0_I2C_SDA_0

0x810c287008

0xac287008

DRV_TYPE [8]

Gen1_I2C

I2C1

PADCTL_G4_GEN1_I2C_SCL_0

0x810c287010

0xac287010

DRV_TYPE [8]

PADCTL_G4_GEN1_I2C_SDA_0

0x810c287018

0xac287018

DRV_TYPE [8]

Gen2_I2C

I2C2

PADCTL_SYS_AO_2_GEN2_I2C_SCL_0

0x0c7a3000

0x8c7a3000

DRV_TYPE [8]

PADCTL_SYS_AO_2_GEN2_I2C_SDA_0

0x0c7a3008

0x8c7a3008

DRV_TYPE [8]

Gen3_I2C

I2C3

PADCTL_SYS_AO_2_GEN3_I2C_SCL_0

0x0c7a3010

0x8c7a3010

DRV_TYPE [8]

PADCTL_SYS_AO_2_GEN3_I2C_SDA_0

0x0c7a3018

0x8c7a3018

DRV_TYPE [8]

Gen5_I2C/PWR_I2C

I2C5

PADCTL_G4_PWR_I2C_SCL_0

0x810c2870d8

0xac2870d8

DRV_TYPE [8]

PADCTL_G4_PWR_I2C_SDA_0

0x810c2870d0

0xac2870d0

DRV_TYPE [8]

Gen7_I2C

I2C7

PADCTL_EDP_GEN7_I2C_SCL_0

0x810c288048

0xac288048

DRV_TYPE [8]

PADCTL_EDP_GEN7_I2C_SDA_0

0x810c288050

0xac288050

DRV_TYPE [8]

Gen9_I2C

I2C9

PADCTL_EDP_GEN9_I2C_SCL_0

0x810c288058

0xac288058

DRV_TYPE [8]

PADCTL_EDP_GEN9_I2C_SDA_0

0x810c288060

0xac288060

DRV_TYPE [8]

Gen11_I2C

I2C11

PADCTL_G5_GEN11_I2C_SCL_0

0x810c2860b0

0xac2860b0

DRV_TYPE [8]

PADCTL_G5_GEN11_I2C_SDA_0

0x810c2860b8

0xac2860b8

DRV_TYPE [8]

Gen12_I2C

I2C12

PADCTL_G2_GEN12_I2C_SCL_0

0x810c2810b0

0xac2810b0

DRV_TYPE [8]

PADCTL_G2_GEN12_I2C_SDA_0

0x810c2810b8

0xac2810b8

DRV_TYPE [8]

Gen13_I2C

I2C13

PADCTL_FSI_G5_GEN13_I2C_SCL_0

0x8110314008

0xb0314008

DRV_TYPE [8]

PADCTL_FSI_G5_GEN13_I2C_SDA_0

0x8110314000

0xb0314000

DRV_TYPE [8]

Gen14_I2C

I2C14

PADCTL_G5_SOC_GPIO138_0

0x810c286000

0xac286000

DRV_TYPE [8]

PADCTL_G5_SOC_GPIO139_0

0x810c286008

0xac286008

DRV_TYPE [8]

Gen15_I2C

I2C15

PADCTL_G3_SOC_GPIO129_0

0x810c282028

0xac282028

DRV_TYPE [8]

PADCTL_G3_SOC_GPIO130_0

0x810c282030

0xac282030

DRV_TYPE [8]

Gen16_I2C

I2C16

PADCTL_G8_SOC_GPIO270_0

0x810c28b000

0xac28b000

DRV_TYPE [8]

PADCTL_G8_SOC_GPIO271_0

0x810c28b008

0xac28b008

DRV_TYPE [8]

FSI I2C PADCTL Tuning from CCPLEX#

Gen13 I2C (FSI) PADCTL registers sit behind the FSI fabric. If you need to tune those PADCTL registers from CCPLEX at runtime, complete the following in addition to the normal I/O tuning flow:

  1. Disable the MB2 firewall for the FSI I2C PADCTL register windows.

    In tegra264-firewall-config-base.dtsi, set exclusion-info = <0>; on every firewall node under FSI_CONTROL_FIREWALL_FSI_PADCTL_A4_BLF that gates FSI I2C PADCTL so the firewall does not block access. The registers needed to be updated are:

    • reg@15447 — READ_CTL_0

    • reg@15448 — READ_CTL_1_0

    • reg@15449 — WRITE_CTL_0

    • reg@15450 — WRITE_CTL_1_0

    • reg@15451 — CTL_SETTING

    Example:

    reg@15447 { /* FSI_FABRIC, FSI_CONTROL_FIREWALL_FSI_PADCTL_A4_BLF, READ_CTL_0 */
    exclusion-info = <0>;
    value = <0x80000000>;
};

  2. Use CHSM debug firmware so firewall audit checks can be skipped.

    Production CHSM firmware enforces firewall auditing. CHSM debug firmware is required to skip those checks while tuning FSI I2C PADCTL registers from CCPLEX. The FSI openbox zip package includes CHSM debug firmware (chsm_fw_debug.bin); you should build your FSI_FW with debug CHSM firmware. For more detail, refer to the Packaging the Binaries into a Blob section in the NVIDIA DriveOS 7.2 FSI Integration Guide.

MB1 BCT Configuration#

For production deployment, configure I2C PADCTL register values in the MB1 BCT configuration file using 32-bit addresses. This method works for all PCT variants.

Configuration File Location#

Edit the BCT configuration file located at:

${NV_WORKSPACE}/drive-foundation/platform-config/hardware/nvidia/platform/t264/automotive/automotive-platform-configs/driveos_customer_config/nv_platforms/<board>/<board>-<sku>/common/bct/prod/tegra264-mb1-bct-prod-<board>-<sku>.dts

Configuration Format#

I2C PADCTL registers are configured using the following format:

<address mask value>, // Comment

Where:

  • address: 32-bit register address (from 32-bit Address column in the register table)

  • mask: Bit mask for the fields to modify (0x00f0f000 for DRVUP and DRVDN fields)

  • value: Register value with desired DRVUP [bits 23:20] and DRVDN [bits 15:12] settings

The mask 0x00f0f000 covers:

  • Bits [23:20] (DRVUP): 0x00f00000

  • Bits [15:12] (DRVDN): 0x0000f000

Example Configuration for I2C0 (GEN0)#

<0xac287004 0x00f0f000 0x00a05000>, // PADCTL_G4_CFG2TMC_GEN0_I2C_SCL_0: CFG_CAL_DRVUP=0xA, CFG_CAL_DRVDN=0x5
<0xac28700c 0x00f0f000 0x00b06000>, // PADCTL_G4_CFG2TMC_GEN0_I2C_SDA_0: CFG_CAL_DRVUP=0xB, CFG_CAL_DRVDN=0x6

Example Configuration for I2C5 (PWR)#

<0xac2870dc 0x00f0f000 0x00808000>, // PADCTL_G4_CFG2TMC_PWR_I2C_SCL_0: CFG_CAL_DRVUP=0x8, CFG_CAL_DRVDN=0x8
<0xac2870d4 0x00f0f000 0x00808000>, // PADCTL_G4_CFG2TMC_PWR_I2C_SDA_0: CFG_CAL_DRVUP=0x8, CFG_CAL_DRVDN=0x8

Calculating Register Values#

To calculate the value field:

  1. Choose DRVUP value (0x0 to 0xF)

  2. Choose DRVDN value (0x0 to 0xF)

  3. Calculate: value = (DRVUP << 20) | (DRVDN << 12)

Example calculations:

DRVUP

DRVDN

Value

Calculation

0xA

0x5

0x00a05000

(0xA << 20) | (0x5 << 12) = 0x00a05000

0x8

0x8

0x00808000

(0x8 << 20) | (0x8 << 12) = 0x00808000

0xF

0xF

0x00f0f000

(0xF << 20) | (0xF << 12) = 0x00f0f000

MB1 BCT Pinmux Configuration#

Alternatively, you can configure I2C pin properties using the pinmux device tree format. This provides more control over individual pin properties beyond drive strength.

Configuration File Location#

Edit the BCT pinmux configuration file located at:

${NV_WORKSPACE}/drive-foundation/platform-config/hardware/nvidia/platform/t264/automotive/automotive-platform-configs/driveos_customer_config/nv_platforms/<board>/<sku>/common/bct/pinmux/tegra264-mb1-bct-pinmux-<board>-<sku>.dtsi

Configuration Format#

I2C PADCTL pins are configured using device tree syntax with the following properties:

<channel>_i2c_<signal>_<pin> {
    nvidia,pins = "<channel>_i2c_<signal>_<pin>";
    nvidia,function = "<function_name>";
    nvidia,pull = <TEGRA_PIN_PULL_NONE | TEGRA_PIN_PULL_DOWN | TEGRA_PIN_PULL_UP>;
    nvidia,tristate = <TEGRA_PIN_DISABLE | TEGRA_PIN_ENABLE>;
    nvidia,enable-input = <TEGRA_PIN_DISABLE | TEGRA_PIN_ENABLE>;
    nvidia,drv-type = <TEGRA_PIN_1X_DRIVER | TEGRA_PIN_2X_DRIVER>;
    nvidia,e-io-od = <TEGRA_PIN_DISABLE | TEGRA_PIN_ENABLE>;
    nvidia,e-lpbk = <TEGRA_PIN_DISABLE | TEGRA_PIN_ENABLE>;
};

The macro definitions are available in:

${NV_WORKSPACE}/drive-foundation/platform-config/hardware/nvidia/tegra/nv-public/include/kernel/dt-bindings/pinctrl/pinctrl-tegra.h

Example Configuration for I2C0 (GEN0)#

gen0_i2c_scl_pw4 {
    nvidia,pins = "gen0_i2c_scl_pw4";
    nvidia,function = "i2c0_clk";
    nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    nvidia,tristate = <TEGRA_PIN_DISABLE>;
    nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
    nvidia,e-io-od = <TEGRA_PIN_ENABLE>;
    nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
};

gen0_i2c_sda_pw5 {
    nvidia,pins = "gen0_i2c_sda_pw5";
    nvidia,function = "i2c0_dat";
    nvidia,pull = <TEGRA_PIN_PULL_NONE>;
    nvidia,tristate = <TEGRA_PIN_DISABLE>;
    nvidia,enable-input = <TEGRA_PIN_ENABLE>;
    nvidia,drv-type = <TEGRA_PIN_1X_DRIVER>;
    nvidia,e-io-od = <TEGRA_PIN_ENABLE>;
    nvidia,e-lpbk = <TEGRA_PIN_DISABLE>;
};

Common Configuration Properties#

Property

Description

nvidia,pull

Pull-up/pull-down configuration: TEGRA_PIN_PULL_NONE, TEGRA_PIN_PULL_DOWN, TEGRA_PIN_PULL_UP

nvidia,tristate

Tristate control: TEGRA_PIN_DISABLE (normal operation), TEGRA_PIN_ENABLE (high-Z)

nvidia,enable-input

Input buffer control: TEGRA_PIN_ENABLE (input), TEGRA_PIN_DISABLE (output only)

nvidia,drv-type

Drive type: TEGRA_PIN_1X_DRIVER (normal, default), TEGRA_PIN_2X_DRIVER (double strength). Can be used to meet SCL rise/fall time or SDA fall time specification limits.

nvidia,e-io-od

Open drain mode: TEGRA_PIN_DISABLE (push-pull), TEGRA_PIN_ENABLE (open drain)

nvidia,e-lpbk

Loopback mode: TEGRA_PIN_DISABLE (normal), TEGRA_PIN_ENABLE (loopback)

Building and Flashing#

After editing the BCT configuration file:

  1. The BCT is rebuilt automatically during bind_partitions.

  2. Create the image:

    ./make/bind_partitions [-b <board_name>] <pct> -p <pct_variant>

  3. Flash the platform normally using the bootburn procedure.

Note

Changes to the BCT configuration require reflashing the platform to take effect.