PCIe Controller Device Tree#

This topic applies only to Linux platforms.

Thor SoC Specific Device Tree Properties#

PCIe controller on Thor SoC is NVIDIA PCIe IP and for RC mode, the driver is based on the host-ecam-generic driver part of Linux Kernel. Therefore, it uses all properties defined in host-generic-pci.yaml. Some of the controller instances are dual mode and can work either in root port mode or endpoint mode, but only one at a time.

RC Mode#

In Thor SoC, only controllers C2, C4, and C5 support the XDMA feature.

Optional Properties#

reg-names: Must include xdma entry to provide Controller XDMA registers.

EP Mode#

In Thor SoC, only controllers C2, C4, and C5 support EP mode. Refer to pci-msi.txt to add MSI interrupt information and iommu.txt to add IOMMU information.

Required Properties#

  • compatible: Thor SoC must contain nvidia,tegra264-pcie-ep.

  • reg: A list of physical base address and length pairs for each set of controller registers. Must contain an entry for each entry in the reg-names property.

  • reg-names: Must include the following entries:

    • xal: Controller’s application logic registers.

    • xal-ep-dm: Controller’s transport layer

    • xtl-ep-pri: Controller’s transport layer private registers.

    • xtl-ep-cfg: Controller’s PCIe config registers.

    • xpl: Controller’s physical layer registers.

    • xdma: Controller’s XDMA registers.

    • addr_space: Used to map remote RC address space

  • interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property.

  • interrupt-names: Must include the following entries:

    • intr: The Tegra interrupt that is asserted for controller interrupts.

  • nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed by controller-id. The following are the controller IDs for each controller.

    • 2: C2

    • 4: C4

    • 5: C5

  • reset-gpios: Must contain a phandle to a GPIO controller followed by GPIO that is being used as PERST input signal. Refer to the pci.txt document.

Optional Properties#

  • nvidia,pex-prsnt-gpios: Must contain a phandle to a GPIO controller followed by GPIO that is being used to support hot plug and unplug via PRSNT# pin.

Examples#

Tegra264 RC mode#

Refer to host-generic-pci.yaml.

Tegra264 EP mode#

pcie-ep@a808460000 {
     status = "disabled";
     compatible = "nvidia,tegra264-pcie-ep";

     reg = <0xa8 0x08460000 0x0 0x00004000
     0xa8 0x08530000 0x0 0x00001000
     0xa8 0x08540000 0x0 0x00001000
     0xa8 0x08541000 0x0 0x00001000
     0xa8 0x08550000 0x0 0x00010000
     0xa8 0x08470000 0x0 0x00010000
     0xc0 0x80000000 0x8 0x00000000>

     reg-names = "xal", "xal-ep-dm", "xtl-ep-pri", "xtl-ep-cfg", "xdma", "xpl", "addr_space";
     interrupts = <GIC_SPI 0x3a4 IRQ_TYPE_LEVEL_HIGH>
     interrupt-names = "intr";
     #address-cells = <0x3>
     #size-cells = <0x2>
     reset-gpios = <&gpio_uphy TEGRA264_UPHY_GPIO(D, 1) GPIO_ACTIVE_LOW>

     iommus = <&smmu1_mmu 0x40000>
     dma-coherent;
     msi-parent = <&its 0x140000>
     nvidia,bpmp = <&bpmp 0x4>
};