Ethernet Server Device Tree Properties#

This document describes the Device Tree (DT) properties for the Ethernet Server.

Ethernet Server DT Properties#

The following Ethernet DT nodes for the Ethernet Server are supported:

  • ethernet@A808910000 for EQOS IP

  • ethernet@a808a10000 for MGBE0 IP

  • ethernet@a808b10000 for MGBE1 IP

  • ethernet@a808d10000 for MGBE2 IP

  • ethernet@a808e10000 for MGBE3 IP

These properties are used to configure the Ethernet Server MAC Device Tree node.

status#

Property Name:

status

Description:

Activation Status of MAC Controller.

Values:

  • okay for Enable

  • disabled for Disable

Resolution:

  • Customizable: Yes

  • Optional: No

nvidia,phy-iface-mode#

Property Name:

nvidia,phy-iface-mode

Description:

PHY interface mode for MGBE IP. This property needs to be populated based on the platform configuration.

Values:

  • 0: XFI 10G (default value if nvidia,phy-iface-mode is out of range. If the default value is not supported by the link partner then functional failures will be observed)

  • 1: XFI 5G

  • 2: USXGMII 10G

  • 3: USXGMII 5G

Resolution:

  • Customizable: Yes

  • Optional: Yes

nvidia,mdio_addr#

Property Name:

nvidia,mdio_addr

Description:

Specify the Physical Layer (PHY) MDIO Address which is used to access PHY registers. This property needs to be populated based on the platform configuration.

Range:

0 to 31. Within the range of 0 to 31 on the MDIO bus, the particular acceptable value relies on the configuration of the platform to which the PHY is connected.

Resolution:

  • Customizable: Yes

  • Optional: Yes

primary_vf_id#

Property Name:

primary_vf_id

Description:

Specifies the primary VF ID for the MAC interface. VF IDs start at 0 for the first VF assigned in the PCT and increment by 1 for each subsequent VF in PCT.

Range:

  • For EQOS: 0 to 3. Default is 0 in case of out of range values.

  • For MGBE: 0 to 4. Default is 0 in case of out of range values.

Resolution:

  • Customizable: Yes

  • Optional: Yes

enable_asil_ioctl#

Property Name:

enable_asil_ioctl

Description:

Add this property in DT for enabling ASIL path for PTP IOCTL execution.

Values:

  • Default is disable.

  • Property present will enable ASIL path for PTP IOCTL execution.

Resolution:

  • Customizable: Yes

  • Optional: Yes

nvidia,pad_auto_cal_pu_offset#

Property Name:

nvidia,pad_auto_cal_pu_offset

Description:

Definition of ETHER_QOS_AUTO_CAL_CONFIG_0 Register: Offset for Pull-Up Value Pad Calibration (2’s Complement). Applicable only for EQOS port.

Range:

0x0-0x1F. 0x0 is default in case property is not present for EQOS IP.

Resolution:

  • Customizable: Yes

  • Optional: No (Used only for EQOS interface)

nvidia,pad_auto_cal_pd_offset#

Property Name:

nvidia,pad_auto_cal_pd_offset

Description:

Definition of ETHER_QOS_AUTO_CAL_CONFIG_0 Register: Offset for Pull-Down Value Pad Calibration (2’s Complement). Applicable only for EQOS port.

Range:

0x0-0x1F. 0x0 is default in case property is not present for EQOS IP.

Resolution:

  • Customizable: Yes

  • Optional: No (Used only for EQOS interface)

nvidia,ptp_m2m_role#

Property Name:

nvidia,ptp_m2m_role

Description:

Ethernet HW role in PTP MAC-TO-MAC time sync. This DT property holds the value to identify role of HW.

Range:

0 to 2. For primary interface: 1, secondary interface: 2, and for inactive interface: 0. Default value is 0 for out of range values.

Resolution:

  • Customizable: Yes

  • Optional: Yes

nvidia,pps_op_ctrl#

Property Name:

nvidia,pps_op_ctrl

Description:

Set PPS output control.

Range:

  • Disable (0): pps output is 1 pulse (of width clk_ptp_i) every second. Default is disable.

  • Enable (1): The binary rollover is 2 Hz, and the digital rollover is 1 Hz.

Resolution:

  • Customizable: Yes

  • Optional: Yes

nvidia,uphy-gbe-mode#

Property Name:

nvidia,uphy-gbe-mode

Description:

Specifies Gigabit Ethernet mode for UPHY. This needs to be populated based on the platform configuration.

Range:

  • 1 for 10G. Default value is 1. This default value might result in functional failure if the UPHY GBE mode is not configured in 10G XFI at UPHY layer.

  • 0 for 5G

Resolution:

  • Customizable: Yes

  • Optional: Yes

nvidia,max-platform-mtu#

Property Name:

nvidia,max-platform-mtu

Description:

Maximum MTU size supported for a platform.

Range:

From 68 to 9000. Default value is 1500 in case of out of range values.

Resolution:

  • Customizable: Yes

  • Optional: Yes

nvidia,pause_frames#

Property Name:

nvidia,pause_frames

Description:

Specifies the pause frame support.

Range:

  • 1 for Enable

  • 0 for Disable. Default value is disable.

Resolution:

  • Customizable: Yes

  • Optional: Yes

nvidia,skip-usxgmii-an#

Property Name:

nvidia,skip-usxgmii-an

Description:

Enable this to skip autonegotiation in USXGMII mode.

Range:

  • 1 to skip AN in usxgmii mode.

  • 0 to enable AN in usxgmii mode.

  • 0 is default in case of invalid value.

Resolution:

  • Customizable: Yes

  • Optional: Yes

nvidia,phy_type#

Property Name:

nvidia,phy_type

Description:

Specifies the type of PHY being used in the form of a string. This value needs to be passed based on the platform configuration, chosen from the below range.

Range:

  • 88Q2221M

  • MVQ3244

  • Nothing if the PHY type is not of above 2

Resolution:

  • Customizable: No (The value of this is constant for a given platform).

  • Optional: Yes

pdma00-num-vdma-channels to pdma07-num-vdma-channels#

Property Name:

pdma00-num-vdma-channels to pdma07-num-vdma-channels

Description:

Number of VDMA channels assigned to the PDMA

Range:

Valid for T264 MGBE - value should be from 1 to OSI_MGBE_MAX_NUM_CHANS

Resolution:

  • Customizable: Yes

  • Optional:

    • For T234: Yes

    • For T264: No

pdma00-vdma-channels to pdma07-vdma-channels#

Property Name:

pdma00-vdma-channels to pdma07-vdma-channels

Description:

List of VMDA channel assigned to the PDMA

Range:

  • Valid for T264 MGBE - List values must range from 0 to OSI_MGBE_MAX_NUM_CHANS

  • List size should match to the corresponding pdmaxx-num-vdma-channels

Resolution:

  • Customizable: Yes

  • Optional:

    • For T234: Yes

    • For T264: No

nvidia,hsi_enable#

Property Name:

nvidia,hsi_enable

Description:

Enable HSI support for the MAC

Range:

  • 1 for Enable. Default is enable.

  • 0 for Disable

Resolution:

  • Customizable: Yes

  • Optional: Yes

nvidia,hsi_err_count_threshold#

Property Name:

nvidia,hsi_err_count_threshold

Description:

Error count threshold beyond which error reporting should be triggered

Range:

  • 1 to UNIT32_MAX

  • Default OSI_HSI_ERR_COUNT_THRESHOLD

Resolution:

  • Customizable: Yes

  • Optional: Yes

nvidia,phyinit_count#

Property Name:

nvidia,phyinit_count

Description:

Number of PHY programming operations after phy initialization.

Range:

0 to 250

Resolution:

  • Customizable: Yes

  • Optional: Yes

nvidia,phyrst_count#

Property Name:

nvidia,phyrst_count

Description:

Number of PHY programming operations after phy reset.

Range:

0 to 250

Resolution:

  • Customizable: Yes

  • Optional: Yes

nvidia,phylup_count#

Property Name:

nvidia,phylup_count

Description:

Number of PHY programming operations after link-up.

Range:

0 to 250

Resolution:

  • Customizable: Yes

  • Optional: Yes

nvidia,phyldown_count#

Property Name:

nvidia,phyldown_count

Description:

Number of PHY programming operations after link-down.

Range:

0 to 250

Resolution:

  • Customizable: Yes

  • Optional: Yes

nvidia,phylpon_count#

Property Name:

nvidia,phylpon_count

Description:

Number of PHY programming operations after low-power on.

Range:

0 to 250

Resolution:

  • Customizable: Yes

  • Optional: Yes

nvidia,phylpoff_count#

Property Name:

nvidia,phylpoff_count

Description:

Number of PHY programming operations after low-power off.

Range:

0 to 250

Resolution:

  • Customizable: Yes

  • Optional: Yes

nvidia,phyinit#

Property Name:

nvidia,phyinit

Description:

Array of PHY programming operations for PHY initialization state. Each entry contains 9 values in the following order:

  1. state - Must be 0

  2. op - Operation type (0=read, 1=write)

  3. macMdioForAddrReg - Value to be written to MAC’s MDIO address register for indirect PHY access

  4. macMdioForDataReg - Value to be written to MAC’s MDIO data register for indirect PHY access

  5. wDelay - Delay in microseconds before operation

  6. waitPoll - Enable polling (0=disable, 1=enable)

  7. pollRegAddr - Value to be written to MAC’s MDIO address register for indirect PHY access for polling feature

  8. pollRegData - Value to be written to MAC’s MDIO data register for indirect PHY access for polling feature

  9. pollExpectedVal - Expected value to match when polling

Range:

  • state: 0

  • op: 0 (read) or 1 (write)

  • Other fields: 32-bit values

  • Number of operations: Up to 250

Resolution:

  • Customizable: Yes

  • Optional: No when corresponding count property (nvidia,phyinit_count) is > 0

nvidia,phyrst#

Property Name:

nvidia,phyrst

Description:

Array of PHY programming operations for PHY reset state. Each entry contains 9 values in the following order:

  1. state - Must be 1

  2. op - Operation type (0=read, 1=write)

  3. macMdioForAddrReg - Value to be written to MAC’s MDIO address register for indirect PHY access

  4. macMdioForDataReg - Value to be written to MAC’s MDIO data register for indirect PHY access

  5. wDelay - Delay in microseconds before operation

  6. waitPoll - Enable polling (0=disable, 1=enable)

  7. pollRegAddr - Value to be written to MAC’s MDIO address register for indirect PHY access for polling feature

  8. pollRegData - Value to be written to MAC’s MDIO data register for indirect PHY access for polling feature

  9. pollExpectedVal - Expected value to match when polling

Range:

  • state: 1

  • op: 0 (read) or 1 (write)

  • Other fields: 32-bit values

  • Number of operations: Up to 250

Resolution:

  • Customizable: Yes

  • Optional: No when corresponding count property (nvidia,phyrst_count) is > 0

nvidia,phylup#

Property Name:

nvidia,phylup

Description:

Array of PHY programming operations for PHY link-up state. Each entry contains 9 values in the following order:

  1. state - Must be 2

  2. op - Operation type (0=read, 1=write)

  3. macMdioForAddrReg - Value to be written to MAC’s MDIO address register for indirect PHY access

  4. macMdioForDataReg - Value to be written to MAC’s MDIO data register for indirect PHY access

  5. wDelay - Delay in microseconds before operation

  6. waitPoll - Enable polling (0=disable, 1=enable)

  7. pollRegAddr - Value to be written to MAC’s MDIO address register for indirect PHY access for polling feature

  8. pollRegData - Value to be written to MAC’s MDIO data register for indirect PHY access for polling feature

  9. pollExpectedVal - Expected value to match when polling

Range:

  • state: 2

  • op: 0 (read) or 1 (write)

  • Other fields: 32-bit values

  • Number of operations: Up to 250

Resolution:

  • Customizable: Yes

  • Optional: No when corresponding count property (nvidia,phylup_count) is > 0

nvidia,phyldown#

Property Name:

nvidia,phyldown

Description:

Array of PHY programming operations for PHY link-down state. Each entry contains 9 values in the following order:

  1. state - Must be 3

  2. op - Operation type (0=read, 1=write)

  3. macMdioForAddrReg - Value to be written to MAC’s MDIO address register for indirect PHY access

  4. macMdioForDataReg - Value to be written to MAC’s MDIO data register for indirect PHY access

  5. wDelay - Delay in microseconds before operation

  6. waitPoll - Enable polling (0=disable, 1=enable)

  7. pollRegAddr - Value to be written to MAC’s MDIO address register for indirect PHY access for polling feature

  8. pollRegData - Value to be written to MAC’s MDIO data register for indirect PHY access for polling feature

  9. pollExpectedVal - Expected value to match when polling

Range:

  • state: 3

  • op: 0 (read) or 1 (write)

  • Other fields: 32-bit values

  • Number of operations: Up to 250

Resolution:

  • Customizable: Yes

  • Optional: No when corresponding count property (nvidia,phyldown_count) is > 0

nvidia,phylpon#

Property Name:

nvidia,phylpon

Description:

Array of PHY programming operations for PHY low-power on state. Each entry contains 9 values in the following order:

  1. state - Must be 4

  2. op - Operation type (0=read, 1=write)

  3. macMdioForAddrReg - Value to be written to MAC’s MDIO address register for indirect PHY access

  4. macMdioForDataReg - Value to be written to MAC’s MDIO data register for indirect PHY access

  5. wDelay - Delay in microseconds before operation

  6. waitPoll - Enable polling (0=disable, 1=enable)

  7. pollRegAddr - Value to be written to MAC’s MDIO address register for indirect PHY access for polling feature

  8. pollRegData - Value to be written to MAC’s MDIO data register for indirect PHY access for polling feature

  9. pollExpectedVal - Expected value to match when polling

Range:

  • state: 4

  • op: 0 (read) or 1 (write)

  • Other fields: 32-bit values

  • Number of operations: Up to 250

Resolution:

  • Customizable: Yes

  • Optional: No when corresponding count property (nvidia,phylpon_count) is > 0

nvidia,phylpoff#

Property Name:

nvidia,phylpoff

Description:

Array of PHY programming operations for PHY low-power off state. Each entry contains 9 values in the following order:

  1. state - Must be 5

  2. op - Operation type (0=read, 1=write)

  3. macMdioForAddrReg - Value to be written to MAC’s MDIO address register for indirect PHY access

  4. macMdioForDataReg - Value to be written to MAC’s MDIO data register for indirect PHY access

  5. wDelay - Delay in microseconds before operation

  6. waitPoll - Enable polling (0=disable, 1=enable)

  7. pollRegAddr - Value to be written to MAC’s MDIO address register for indirect PHY access for polling feature

  8. pollRegData - Value to be written to MAC’s MDIO data register for indirect PHY access for polling feature

  9. pollExpectedVal - Expected value to match when polling

Range:

  • state: 5

  • op: 0 (read) or 1 (write)

  • Other fields: 32-bit values

  • Number of operations: Up to 250

Resolution:

  • Customizable: Yes

  • Optional: No when corresponding count property (nvidia,phylpoff_count) is > 0

nvidia,mdc-cr#

Property Name:

nvidia,mdc-cr

Description:

MDC Clock Range (CR) value for MDIO clock configuration

Range:

EQOS Normal Mode (0-7):

  • 0: CSR 60-100 MHz (div=42)

  • 1: CSR 100-150 MHz (div=62)

  • 2: CSR 20-35 MHz (div=16)

  • 3: CSR 35-60 MHz (div=26)

  • 4: CSR 150-250 MHz (div=102)

  • 5: CSR 250-300 MHz (div=124)

  • 6: CSR 300-500 MHz (div=204)

  • 7: CSR 500-800 MHz (div=324)

EQOS High Speed Mode (8-F):

  • 8: div=4

  • 9: div=6

  • A: div=8

  • B: div=10

  • C: div=12

  • D: div=14

  • E: div=16

  • F: div=18

MGBE Normal Mode (0-7):

  • 0: CSR 100-150 MHz (div=62)

  • 1: CSR 150-250 MHz (div=102)

  • 2: CSR 250-300 MHz (div=122)

  • 3: CSR 300-350 MHz (div=142)

  • 4: CSR 350-400 MHz (div=162)

  • 5: CSR 400-500 MHz (div=202)

  • 6-7: Reserved

MGBE High Speed Mode (8-F):

  • 8: div=4

  • 9: div=6

  • A: div=8

  • B: div=10

  • C: div=12

  • D: div=14

  • E: div=16

  • F: div=18

Default:

  • EQOS: 6 (CSR 300-500 MHz, div=204)

  • MGBE: 5 (CSR 400-500 MHz, div=202)

Resolution:

  • Customizable: Yes

  • Optional: Yes

Example DT Node#

ethernet@XXXXXXXXXX {
    compatible = "nvidia,tegra264-mgbe";

    nvidia,num-mtl-queues = <10>;
    nvidia,mtl-queues = <0 1 2 3 4 5 6 7 8 9>;
    nvidia,tc-mapping = <0 1 2 3 4 5 6 7 0 1>;
    nvidia,tx-queue-prio = <0 1 2 3 4 5 6 7 0 0>;
    nvidia,rx-queue-prio = <0x1 0x2 0x4 0x8 0x10 0x20 0x40 0x80 0x0 0x0>;
    nvidia,rxq_enable_ctrl = <2 2 2 2 2 2 2 2 2 2>;
    nvidia,dcs-enable = <0x1>;
    nvidia,phy_type = "88Q2221M";
    nvidia,pad_auto_cal_pd_offset = <0x0>;
    nvidia,pad_auto_cal_pu_offset = <0x0>;

    pdma00-num-vdma-channels = <1>;
    pdma00-vdma-channels = <0>;
    pdma01-num-vdma-channels = <1>;
    pdma01-vdma-channels = <1>;
    pdma02-num-vdma-channels = <1>;
    pdma02-vdma-channels = <2>;
    pdma03-num-vdma-channels = <1>;
    pdma03-vdma-channels = <3>;
    pdma04-num-vdma-channels = <1>;
    pdma04-vdma-channels = <4>;
    pdma05-num-vdma-channels = <1>;
    pdma05-vdma-channels = <5>;
    pdma06-num-vdma-channels = <1>;
    pdma06-vdma-channels = <6>;
    pdma07-num-vdma-channels = <1>;
    pdma07-vdma-channels = <7>;

    nvidia,instance_id = <4>;
    nvidia,ptp_m2m_role = <2>;

    nvidia,phyinit_count = <2>;
    nvidia,phyinit = <0 1 0x1 0x100 100 1 0x2 0x3 0x1>,
                     <0 0 0x2 0x0 50 0 0x0 0x0 0x0>;
    nvidia,phyrst_count = <1>;
    nvidia,phyrst = <1 1 0x0 0x8000 500 1 0x0 0x8000 0x0>;
    nvidia,phylup_count = <1>;
    nvidia,phylup = <2 0 0x1 0x0 100 1 0x1 0x4 0x4>;
};