NVIDIA DRIVE AV Audio Ownership Configuration#

The audio ownership management is managed by the pct_config.h file.

${NV_WORKSPACE}/hardware/nvidia/platform/t2xx/automotive/pct/drive_av/guest_config.h

The following section shows an example configuration for audio ownership for a guest.

.ape_cfg = {
    .stream_id = TEGRA_SID_APE,
    .is_adsp_enabled = 0,
    .adsp_stream_id = TEGRA_SID_APE + 0x6,
    .adma_assignment_inst = {
        ADMA_PAGE1, {ADMA_CH1, ADMA_CH2, ADMA_CH3, ADMA_CH4, ADMA_CH5, ADMA_CH6, ADMA_CH7, ADMA_CH8,
            ADMA_CH9, ADMA_CH10, ADMA_CH11, ADMA_CH12, ADMA_CH13, ADMA_CH14, ADMA_CH15, ADMA_CH16,
            ADMA_CH17, ADMA_CH18, ADMA_CH19, ADMA_CH20, ADMA_CH21, ADMA_CH22, ADMA_CH23, ADMA_CH24,
            ADMA_CH25, ADMA_CH26, ADMA_CH27, ADMA_CH28, ADMA_CH29, ADMA_CH30, ADMA_CH31, ADMA_CH32,
            ADMA_CH33, ADMA_CH34, ADMA_CH35, ADMA_CH36, ADMA_CH37, ADMA_CH38, ADMA_CH39, ADMA_CH40,
            ADMA_CH41, ADMA_CH42, ADMA_CH43, ADMA_CH44, ADMA_CH45, ADMA_CH46, ADMA_CH47, ADMA_CH48}, ADMAIF1, ADMAIF24
     },
     .ape_irq_inst[0] = { INT_ADMA_EOT0 , CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[1] = { INT_ADMA_EOT0 + 1, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[2] = { INT_ADMA_EOT0 + 2, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[3] = { INT_ADMA_EOT0 + 3, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[4] = { INT_ADMA_EOT0 + 4, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[5] = { INT_ADMA_EOT0 + 5, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[6] = { INT_ADMA_EOT0 + 6, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[7] = { INT_ADMA_EOT0 + 7, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[8] = { INT_ADMA_EOT0 + 8, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[9] = { INT_ADMA_EOT0 + 9, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[10] = { INT_ADMA_EOT0 + 10, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[11] = { INT_ADMA_EOT0 + 11, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[12] = { INT_ADMA_EOT0 + 12, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[13] = { INT_ADMA_EOT0 + 13, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[14] = { INT_ADMA_EOT0 + 14, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[15] = { INT_ADMA_EOT0 + 15, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[16] = { INT_ADMA_EOT0 + 16, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[17] = { INT_ADMA_EOT0 + 17, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[18] = { INT_ADMA_EOT0 + 18, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[19] = { INT_ADMA_EOT0 + 19, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[20] = { INT_ADMA_EOT0 + 20, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[21] = { INT_ADMA_EOT0 + 21, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[22] = { INT_ADMA_EOT0 + 22, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[23] = { INT_ADMA_EOT0 + 23, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[24] = { INT_ADMA_EOT0 + 24, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[25] = { INT_ADMA_EOT0 + 25, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[26] = { INT_ADMA_EOT0 + 26, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[27] = { INT_ADMA_EOT0 + 27, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[28] = { INT_ADMA_EOT0 + 28, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[29] = { INT_ADMA_EOT0 + 29, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[30] = { INT_ADMA_EOT0 + 30, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[31] = { INT_ADMA_EOT0 + 31, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[32] = { INT_ADMA_EOT0 + 32, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[33] = { INT_ADMA_EOT0 + 33, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[34] = { INT_ADMA_EOT0 + 34, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[35] = { INT_ADMA_EOT0 + 35, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[36] = { INT_ADMA_EOT0 + 36, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[37] = { INT_ADMA_EOT0 + 37, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[38] = { INT_ADMA_EOT0 + 38, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[39] = { INT_ADMA_EOT0 + 39, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[40] = { INT_ADMA_EOT0 + 40, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[41] = { INT_ADMA_EOT0 + 41, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[42] = { INT_ADMA_EOT0 + 42, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[43] = { INT_ADMA_EOT0 + 43, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[44] = { INT_ADMA_EOT0 + 44, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[45] = { INT_ADMA_EOT0 + 45, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[46] = { INT_ADMA_EOT0 + 46, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .ape_irq_inst[47] = { INT_ADMA_EOT0 + 47, CPU1_INTERFACE, SET_ENABLE, LEVEL_TRIGGER},
     .num_adma_irq_routed = 48,
     .ape_ahub_resource_inst = {
         {
             ADMAIF1, ADMAIF2, ADMAIF3, ADMAIF4, ADMAIF5, ADMAIF6, ADMAIF7, ADMAIF8,
             ADMAIF9, ADMAIF10, ADMAIF11, ADMAIF12, ADMAIF13, ADMAIF14, ADMAIF15, ADMAIF16,
             ADMAIF17, ADMAIF18, ADMAIF19, ADMAIF20, ADMAIF21, ADMAIF22, ADMAIF23, ADMAIF24,
             AMX1, AMX2, AMX3, AMX4, AMX5, AMX6,
             ADX1, ADX2, ADX3, ADX4, ADX5, ADX6,
             I2S1, I2S2, I2S3, I2S4, I2S5, I2S6, I2S7, I2S8,
             SFC1, SFC2, SFC3, SFC4, MVC1, MVC2,
             ASRC1, AMIXER1
         },
     },
     .vinterface = {
         .queues = RESOURCE_POOL(162, 1),
     },
 },

The ape_cfg structure contains the elements for audio ownership configuration. Each member of this structure is described below.

  • stream_id : The APE stream ID used by each guest VM. Every guest VM must have a unique APE stream ID, starting from TEGRA_SID_APE. This can be incremented by 1 for each further guest VM.

  • is_adsp_enabled : Set to 1 if the ADSP is enabled, otherwise set to 0.

  • adsp_stream_id : The APE stream ID used by the ADSP. This should be set to TEGRA_SID_APE+6 as per default hardware configuration.

  • adma_assignment_inst : This specifies the ADMA page and channel assignments for each of the guest VM, along with the corresponding ADMAIF instances. This must align with the ADMA page configuration on the guest VM DT. Each guest VM will be allowed to access only the specified ADMA page here. That ADMA page will have only the specified channels enabled.

  • ape_irq_inst : This specifies the IRQ routing corresponding to each ADMA channel. Whichever channels are allocated for this VM, should have a corresponding IRQ entry here. INT_ADMA_EOT0 corresponds to ADMA_CH1, INT_ADMA_EOT0+1 corresponds to ADMA_CH2, and so on. CPU Interface should be chosen as per the interface used by this particular guest VM. IRQ trigger should be kept as level trigger as shown in the example.

  • num_adma_irq_routed : The number of ADMA IRQs routed to this guest VM.

  • ape_ahub_resource_inst : The list of AHUB module instances that are allocated to this guest VM.

  • vinterface.queues : This is the IVC queue number allocated to the guest VM for communication between the guest VM audio virtualized drivers and audio server.

For each guest VM, one instance of the ape_cfg is required, containing the audio resource allocation for that guest VM.