Bootloader

The following sections describe bootloader programming.

DRAM Training Restriction

DVFS tables are now part of BPMP-FW-DTB. A separate binary MEMDTB holds the DVFS tables for all ramcodes and the training table corresponding to device ramcode is loaded by MB2. BPMP-FW code integrates MSS code drop, which supports both hardware and software based periodic training. The varient used is defined by the calibration data (EMC timing tables). For chips up to TH500, the timing tables are part of BPMP-FW -DDTB. Starting from T264, timing tables are part of a common DRAM configuration and is passed to software in membct and memdtb partitions. The BPMP-FW signals to HSM and halts boot if a software-based periodic training is needed for a DRAM DVFS table entry.

• DRIVE AGX Boot Flow
  • Boot ROM
  • Microboot 1 and PSC-BL1
  • Microboot 2
  • Authentication and Validation of Binaries
  • Grouping of Boot Images
  • Grouping a Secure Boot Chain
• Using the Bootloader Recovery Mechanism
  • Recovery Mechanism Boot Chains
  • Boot Recovery Mechanism Flow
• Ratchet Checks
  • Ratchet Check for NVIDIA Owned Software Components
• Passing Ratchet Status to Guest OS
• Lock Fuse Burning
• Passing Customer Data to Guest OSes
• Configuring MB1 Boot Configuration Table
  • Understanding the MB1 Boot Configuration Table
  • Configuring the Pinmux and GPIO
  • Configuring the Prod Setting
  • Configuring Pad Voltage Setting
  • Configuring the PMIC Setting
  • AO Block Parameters
  • Configuring the Security Configuration Registers
  • Miscellaneous Configurations
  • Enabling Memory Latent Fault Test
• Restricting Power Controls
• Flashtool Interface for ECID