Digital Audio Port

Thor Series SoC provides eight Inter-IC Sound (I2S) or Digital Audio Port (DAP) interfaces. The I2S controller implements full-duplex and bidirectional and single direction point-to-point serial interfaces. It can interface with I2S-compatible devices. I2S controller can operate both as initiator and target.

Required Equipment

The following equipment is required:

• Oscilloscope and probe: any oscilloscope and high-impedance probe with a bandwidth of 100 MHz or greater.

• Software tools:

  • devmem2 for Linux

  • amixer for Linux

  • dw/mw for BPMP

Measurement

Measurement consists of the following steps:

1. Attach the probes to the DUT, as close to the end point as possible—nearest to the receiver side.

2. Power on the DUT.

3. Configure the DUT to drive traffic.

4. Check waveforms on the scope and modify the drive strength control register if the output signal does not meet specifications and signal integrity requirements.

Controller and Port Name

The following table lists DAP controllers in Thor Series SoC and the related signal strength registers.

Port Name	Signal	Address (64bit)	Instance	CFG_CAL_DRVUP	CFG_CAL_DRVDN
DAP1	I2S1_SCLK	0x810c286094	PADCTL_G5_CFG2TMC_DAP1_SCLK_0	[23:20]	[15:12]
I2S1_SDATA_OUT	0x810c2860a4	PADCTL_G5_CFG2TMC_DAP1_OUT_0
I2S1_SDATA_IN	0x810c28609c	PADCTL_G5_CFG2TMC_DAP1_IN_0
I2S1_LRCK	0x810c2860ac	PADCTL_G5_CFG2TMC_DAP1_FS_0
DAP2	I2S2_SCLK	0x810c28704c	PADCTL_G4_CFG2TMC_DAP2_CLK_0	[23:20]	[15:12]
I2S2_SDATA_OUT	0x810c28705c	PADCTL_G4_CFG2TMC_DAP2_DOUT_0
I2S2_SDATA_IN	0x810c287054	PADCTL_G4_CFG2TMC_DAP2_DIN_0
I2S2_LRCK	0x810c287044	PADCTL_G4_CFG2TMC_DAP2_FS_0
DAP3	I2S3_SCLK	0x810c28b014	PADCTL_G8_CFG2TMC_SOC_GPIO272_0	[23:20]	[15:12]
I2S3_SDATA_OUT	0x810c28b01c	PADCTL_G8_CFG2TMC_SOC_GPIO273_0
I2S3_SDATA_IN	0x810c28b024	PADCTL_G8_CFG2TMC_SOC_GPIO274_0
I2S3_LRCK	0x810c28b02c	PADCTL_G8_CFG2TMC_SOC_GPIO275_0
DAP4	I2S4_SCLK	0x810c28603c	PADCTL_G5_CFG2TMC_DAP4_SCLK_0	[23:20]	[15:12]
I2S4_SDATA_OUT	0x810c286034	PADCTL_G5_CFG2TMC_DAP4_DOUT_0
I2S4_SDATA_IN	0x810c286044	PADCTL_G5_CFG2TMC_DAP4_DIN_0
I2S4_LRCK	0x810c28604c	PADCTL_G5_CFG2TMC_DAP4_FS_0
DAP5	I2S5_SCLK	0x810c28200c	PADCTL_G3_CFG2TMC_SOC_GPIO125_0	[23:20]	[15:12]
I2S5_SDATA_OUT	0x810c28203c	PADCTL_G3_CFG2TMC_SOC_GPIO131_0
I2S5_SDATA_IN	0x810c282024	PADCTL_G3_CFG2TMC_SOC_GPIO128_0
I2S5_LRCK	0x810c28204c	PADCTL_G3_CFG2TMC_SOC_GPIO133_0
DAP6	I2S6_SCLK	0x810c28602c	PADCTL_G5_CFG2TMC_DAP6_SCLK_0	[23:20]	[15:12]
I2S6_SDATA_OUT	0x810c28601c	PADCTL_G5_CFG2TMC_DAP6_DOUT_0
I2S6_SDATA_IN	0x810c286014	PADCTL_G5_CFG2TMC_DAP6_DIN_0
I2S6_LRCK	0x810c286024	PADCTL_G5_CFG2TMC_DAP6_FS_0
DAP7	I2S7_SCLK	0x810c28709c	PADCTL_G4_CFG2TMC_SOC_GPIO176_0	[23:20]	[15:12]
I2S7_SDATA_OUT	0x810c2870ac	PADCTL_G4_CFG2TMC_SOC_GPIO178_0
I2S7_SDATA_IN	0x810c28706c	PADCTL_G4_CFG2TMC_SOC_GPIO170_0
I2S7_LRCK	0x810c287064	PADCTL_G4_CFG2TMC_PWM10_0
DAP8	I2S8_SCLK	0x810c286074	PADCTL_G5_CFG2TMC_SOC_GPIO152_0	[23:20]	[15:12]
I2S8_SDATA_OUT	0x810c28607c	PADCTL_G5_CFG2TMC_SOC_GPIO153_0
I2S8_SDATA_IN	0x810c2860c4	PADCTL_G5_CFG2TMC_SOC_GPIO350_0
I2S8_LRCK	0x810c286084	PADCTL_G5_CFG2TMC_SOC_GPIO155_0
AUD_MCLK	AUD_MCLK	0x810c28608c	PADCTL_G5_CFG2TMC_AUD_MCLK_0	[23:20]	[15:12]

Drive Strength Adjustment

DAP drive strength adjustment occurs by providing offsets to the pull-up and pull-down pad.

1. Set up an oscilloscope to probe the respective DAP pin.

2. Boot up the DUT and open a command console for UART or over Ethernet from the DUT.

3. Configure the DUT to drive traffic.

4. Check waveforms on the scope and modify the drive strength control registers if the output signal does not meet specifications and signal integrity requirements.

5. Tuning is complete when signals meet specifications and signal integrity requirements. Contact NVIDIA Application Engineering and TSE to update the golden register (GR).

Examples

Note

The examples are for illustration purposes only. Values should not be considered as reference.

This example explains how to generate an audio signal and apply the specific offsets to the pull-up and pull-down codes: CFG_CAL_DRVUP and CFG_CAL_DRVDN = 0x0 or 0xf.

1. Enable DAP2 or DAP3 port using commands the following Linux commands:

#amixer cset name='I2S2 Mux' 'ADMAIF1'
#amixer cset name='I2S3 Mux' 'ADMAIF1'

Confirm that the commands return results without errors.

Note

The name of controls and contents for amixer may be different according to the board design. Work with an audio software engineer to obtain the right amixer settings.

The following commands are helpful in finding the settings: * #amixer contents * #amixer controls

2. Enable DOUT, FS by playing WAV:

# speaker-test -Dhw:0,0 -c 8 -r 48000 -F S32_LE -t sine -f 1000&

Check to see if DOUT or FS toggle.

3. Use different CFG_CAL_DRVUP or CFG_CAL_DRVDN values to see if waveform changes. 1. Set DAP2 or DAP3 SCLK with CFG_CAL_DRVUP and CFG_CAL_DRVDN = 0xf.

For DAP2_SCLK:

#devmem2 0x810c28704c w 0x0f0f000

For DAP3_SCLK:

#devmem2 0x810c28b014 w 0x0f0f000

2. Set DAP2 or DAP3 FS with DRVUP and DRVDN = 0xf.

For DAP2_FS:

#devmem2 0x810c287044 w 0x0f0f000

For DAP3_FS:

#devmem2 0x810c28b02c w 0x0f0f000

3. Set DAP2 or DAP3 DOUT with CFG_CAL_DRVUP and CFG_CAL_DRVDN = 0xf.

For DAP2_DOUT:

devmem2 0x810c28705c w 0x0f0f000

For DAP3_DOUT:

devmem2 0x810c28b01c w 0x0f0f000

Final Check

After the settings are updated in the driver/MB1, verify that the tuned settings are applied for each pad and across the frequencies to be used.

Contact NVIDIA Application Engineering if NVIDIA support is required to obtain the tests to exercise and measure relevant waveforms. Customers are required to ensure that there is enough margin for a particular mode on the platform being tested.