Configuration#

EPS Configuration#

Configuration header - Eps_Cfg.h

This header can be used to disable hardware errors associated with any IP by adding the corresponding reporter ID in this list.

SS_EPS_DISABLE_ERR_LIST - List of ErrorCodes to be disabled completely. Both interrupts and SOC error pin assertion are disabled for the HSM errors corresponding to the error codes mentioned in the list.

#define SS_EPS_DISABLE_ERR_LIST {\
    SS_ERR_FSIHSM_FSI_SE_UE, \
    SS_ERR_FSIHSM_FSI_DMA_UE, \
    SS_ERR_SCEHSM_CAR_34_UE \
}

Use this header to disable SoC error pin assertion for individual hardware HSM error by adding the corresponding error code in this list.

SS_EPS_SOCERRPIN_DISABLE_LIST - List of errors for which only SoC error assertion needs to be disabled. Add ErrorCode to be disabled to this list. Sample list:

#define SS_EPS_DISABLE_ERR_LIST {\
     SS_ERR_FSIHSM_FSI_DMA_UE, \
     SS_ERR_FSIHSM_FSI_CPU_CNA_2_UE, \
     SS_ERR_SCEHSM_CAR_34_UE \
  }

Note: SOC_ERROR toggling is the de-assert state. SOC_ERROR pin toggling is enabled in Eps_init->HSM_init.

SS_EPS_EC_CE_THRESHOLD_LIST

Use this header to change the corrected error threshold value for an error collator. To update the threshold value, add the new threshold value along with the ErrorCode of the HSM error connected to the error collator.

For example, to change the corrected error threshold for SCE Error collator and FSI CAR error collator to 42 and 99 respectively, the list is:

#define SS_EPS_EC_CE_THRESHOLD_LIST {\
{SS_ERR_SCEHSM_SCE_CLUSTER_CE, 42U},\
{SS_ERR_FSIHSM_FSI_CAR_CE, 99U}\
}

By default, the threshold value for all error collators is set to 0. The error ID in the list must be connected to an error collator, and the value of threshold must be less than 255.

SS_EPS_SW_ERR_DISABLE_LIST

Use this list to disable software-reported errors. Both error notification and SoC error pin assertion are disabled for the errors in the list. Include the reporter ID and error code to be disabled.

Sample List -

#define SS_EPS_SW_ERR_DISABLE_LIST {\
{SW_REPORTERID_FSI_COMMON, 0x568732},\
{SW_REPORTERID_BPMP, 0x500034} \
}

SS_EPS_EC_DISABLE_LIST

List of errors in error collators to be disabled. Enter the ErrorCode connected to EC and index of the ec error to be disabled in this format as below sample list.

Sample List -

#define SS_EPS_EC_DISABLE_LIST {\
  {SS_ERR_SCEHSM_BPMP_CLUSTER_UE, 0x2},\
  {SS_ERR_FSIHSM_FSI_CPU_UE, 0x4}\
}

ErrorCode in the list must be connected to an error collator.

Note

Rebuild FSI software after the configuration update.

SPI 2 Satellite Configuration#

CddSpi_Cfg.h configuration header.

The file contains configurations for the FSI SPI controller. These configurations should not change. They are matched with MCU SPI controller configuration. If the CDD SPI configuration changes, ensure that the configuration changes in FSI match with corresponding changes on MCU SPI. Refer to the NVIDIA DriveOS MCU Software Modules Integration Guide for MCU SPI configuration.

Configuration parameter

Description

Default Value

SPI_CS_POL_INACTIVE_N

The inactive value of SPI Master Chip Select value that is connected to the SPI Slave

1 (High)

SPI_CMD_EN_LE_BIT

Enable/Disable Little Endian Bit

1 (Enabled)

SPI_CMD_EN_LE_BYTE

Enable/Disable Little Endian Byte

1 (Enabled)

FSI SPI core clock is configured to 40 MHz. The maximum clock rate that can be configured on MCU SPI is 26.67 MHz.

FSI SPI controller is configured for data width: 32 bits and transfer start from LSBit first.

CCPLEX#

Safety Services configuration DT

SS_ErrorReportingConfig DT node must be enabled at the Guest OS level. The DT file name is ${NV_WORKSPACE}/drive-foundation/platform-config/hardware/nvidia/platform/t264/automotive/kernel-dts/p3960/p3960-10/tegra264-p3960-0010-linux-gos.dtsi.

Configuration changes in the DT are applied over and above the static configuration from FSI EPS configuration header file. Example: If a reporter ID is not configured to be disabled based on the FSI configuration header but it is configured to be disabled based on CCPLEX DT configuration, then the reporter ID is disabled but only after Guest OS boot.

For CCPLEX, use the Guest OS DT file to configure hardware error reporting related parameters.

SEC_Threshold

List of EC Threshold for error codes pertaining to corrected EC errors. SEC_Threshold_count must be updated appropriately after updating SEC_Threshold list.

Sw_Errors

To disable reporting of software errors, add the reporter ID and error codes in the Sw_Errors DT property. Sw_Errors_count DT property must be updated appropriately after modification to the Sw_Errors.

Disable_EC

List of error collator errors to be disabled. Entry should be <ErrorCode ECIndex>. ErrorCode is for the HSM error, which is connected to the EC where error needs to be disabled, and EC_Index is index of the EC error to be disabled. Disable_EC_count DT property should be updated appropriately after modification to the Disable_EC.

List_of_ErrCode_to_disable_error

List of Error Codes (corresponding to a HSM error line) for which error detection and SoC pin assertion must be disabled completely. List_of_ErrCode_to_disable_error_count must be updated appropriately after modification to the List_of_ErrCode_to_disable_error.

List_of_ErrCode_to_disable_SOC_Err_Pin

List of Error codes for which SOC pin assertion from HSM must be disabled. List_of_ErrCode_to_disable_SOC_Err_Pin_count must be updated appropriately after modification to the List_of_ErrCode_to_disable_SOC_Err_Pin.

HSM_Timer

Timeout (in micro seconds) period after which SOC error pin is asserted.

TSC_MON enable/disable :

TSC_MON_Enable - TSC Monitor enable/disable. (Enable:0x1 Disable:0x0) TSC Mon must always be disabled in Linux.

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