DRAM Error-Correcting Code

SoC external memory (DRAM) Error-Correcting Code (ECC) is a safety-related feature implemented in the SoC.

DRAM is protected from bit-flip errors using the ECC. The ECC code corrects single-bit errors and detects double-bit errors.

ECC Bits Storage

Automotive Platform support System ECC where the ECC is bits stored in a separate location in the DRAM and does not impact the DRAM capability for Software access.

Error Detection

For every write to the DRAM, the corresponding ECC bits are also updated. For every read from the DRAM, the ECC of the read data is compared with the stored ECC, and any mismatch results in an error. SoC DRAM ECC implementation has the capability to correct single-bit errors in data/ECC bits, detect the double-bit errors in data/ECC bits, and detect errors in address bits.

The error reporting details contain the information on the exact “address” in which the error was detected.

DRAM Size Impact

There is no impact to the available DRAM Size as the ECC storage is at a separate location in the DRAM.

DRAM Bandwidth Impact

ECC does not require extra bandwidth.

DRAM ECC Enabled Boot on DRIVE Development Platform Pegasus

• DRAM ECC is enabled by default in the Safety build for all production PCT variants.

• DRAM ECC is disabled by default in the non-Safety build, development PCT variants and can be enabled by passing -E flashing option.

Confirming the DRAM ECC Enabled Boot

Read the register 0x02c11880 and confirm that it is 0x1 (indicates DRAM ECC is enabled).

From BPMP-FW console run below command:

] dw 0x8108861014 4 0x8108861014: 16th bit must be set.

For instructions on binding to enable DRAM ECC, see Bind Steps for NVIDIA Orin System on a Chip (SoC) under Flashing Basics in the NVIDIA DriveOS 6.0 SDK Developer Guide.