Display Serializer

Configuring Video Timings

For both SST and MST mode, the mode timings that are used for each stream must be configured in Device Tree. Only one mode timing can be specified at a time for each video stream. The timings that are exposed in the EDIDs of the serializer and the panels connected to the downstream deserializer are completely ignored.

An example Device Tree fragment is shown below. In this example, a standard 1920x1080 at 60 Hz timing is specified for the first video stream, and a 1280x720 at 60 Hz timing is specified for the second video stream:

\ {
    display@13800000 {
        display-timings {
            display-connector-0 {
                dcb-index = <0>;

                stream-0 {
                    timings-phandle = <&mode0>;
                };

                stream-1 {
                    timings-phandle = <&mode1>;
                };
            };
        };

        mode0: 1920-1080-60Hz {
            clock-frequency-khz = <148500>;
            hactive = <1920>;
            vactive = <1080>;
            hfront-porch = <88>;
            hback-porch = <148>;
            hsync-len = <44>;
            vfront-porch = <4>;
            vback-porch = <36>;
            vsync-len = <5>;
            rrx1k = <60000>;
            pps-data = [
                11 00 00 89 30 80 04 38
                07 80 04 38 03 c0 03 c0
                02 00 03 58 00 20 73 3e
                00 0d 00 0f 00 1d 00 0e
                18 00 10 f0 03 0c 20 00
                06 0b 0b 33 0e 1c 2a 38
                46 54 62 69 70 77 79 7b
                7d 7e 01 02 01 00 09 40
                09 be 19 fc 19 fa 19 f8
                1a 38 1a 78 22 b6 2a b6
                2a f6 2a f4 43 34 63 74
                00 00 00 00 00 00 00 00
                00 00 00 00 00 00 00 00
                00 00 00 00 00 00 00 00
                00 00 00 00 00 00 00 00
                00 00 00 00 00 00 00 00 ];
        };

        mode1: 1280-720-60Hz {
            clock-frequency-khz = <74250>;
            hactive = <1280>;
            vactive = <720>;
            hfront-porch = <110>;
            hback-porch = <220>;
            hsync-len = <40>;
            vfront-porch = <5>;
            vback-porch = <20>;
            vsync-len = <5>;
            rrx1k = <60000>;
        };
    };
};

Each "display-connector" can only have up to two (2) "stream" nodes. Note that it is fine to specify two (2) "stream" nodes even if the display serializer operates in SST mode because only the first "stream" node is consumed by the display driver. The extra node is ignored.

Configuring the Maxim DP Serializer Driver

If you are using the NVIDIA reference Maxim DP serializer driver, there are various ways to configure the driver by using Device Tree. As shown in the following example, a Device Tree fragment configures the Maxim DP serializer chip in MST mode:

i2c@31e0000 {
    status = "okay";
    maxim_ser: max_gmsl_dp_ser@40 {
        compatible = "maxim,max_gmsl_dp_ser";
        reg = <0x40>;
        status = "okay";
        max_gmsl_dp_ser-pwrdn = <&tegra_main_gpio TEGRA234_MAIN_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
        ser-errb = <&tegra_main_gpio TEGRA234_MAIN_GPIO(G, 7) 0>;
        dprx-link-rate = <0x1e>;
        dprx-lane-count = <0x4>;
        enable-mst;
        mst-payload-ids  = <0x1 0x3 0x2 0x4>;
        gmsl-stream-ids  = <0x0 0x1 0x2 0x3>;
        gmsl-link-select = <0x0 0x0 0x1 0x1>;        
        enable-dp-fec;
        enable-dsc = <0 1>;
        enable-gmsl-fec = <0 1>;
        enable-gmsl3 = <0 1>; 

        
    };
};

A description of each of the preceding properties:

• Required properties:
  • compatible: Must be "maxim,max_gmsl_dp_ser".
  • reg: I2C address of the Maxim DP display serializer.
  • max_gmsl_dp_ser-pwrdn: GPIO pin number of the PWRDN pin. This pin is used to power up the Maxim DP display serializer chip.
  • gmsl-link-select: This property is an array of four unsigned 8-bit values that determines the GMSL output link to enable for each video pipe X, Y, Z, and U. The possible values for each pipe are:

    • 0x0 (Link A)
    • 0x1 (Link B)
    • 0x2 (Link A + B)
• Optional properties:

  • dprx-link-rate: Configures the DP link rate of the serializer chip.

    The default value is 0x1E (HBR3). The possible values are:

    • 0xA (HBR)
    • 0x14 (HBR2)
    • 0x1E (HBR3)

  • dprx-lane-count: Configures the DP lane count of the serializer chip.

    The default value is 0x4. The possible values are:

    • 0x1
    • 0x2
    • 0x4

  • ser-errb: GPIO pin number of the ERRB pin. This pin is used for error and fault reporting by the serializer chip.

  • enable-mst: This is a Boolean property. If this property is present, the driver will enable MST mode.

  • mst-payload-ids: This property is an array of four unsigned 8-bit values, which represent MST payload IDs of pipe X, Y, Z, U. This property is mandatory if the enable-mst property is mentioned in dt.

  • gmsl-stream-ids: This property is an array of four unsigned 8-bit values, which represent GMSL stream IDs of pipe X, Y, Z, U. This property is mandatory if enable-mst property is mentioned in dt.

  • enable-dp-fec: This is a Boolean property. When this property is present, the driver will enable FEC on the DP link if the serializer chip supports it.
  • enable-dsc: This property is an array of two 32-bit values, where each value indicates whether DSC is enabled or not. The first entry corresponds to video pipe X, and the second entry corresponds to video pipe Y. DSC is only supported on pipe X currently.
  • enable-gmsl-fec: This property is an array of two 32-bit values, where each value indicates whether FEC is enabled on the GMSL link. The first entry corresponds to GMSL Link A, and the second entry corresponds to GMSL Link B.
  • enable-gmsl3: This is a boolean property. When this property is set, GMSL3 capabilities are enabled.

Modeset Limitations

The Maxim DP display serializers do not support dynamic mode changes in MST mode without requiring a reset of the serializer chip in-between. In this context, a mode change refers to changing the number of video streams and/or the display timings that are used for each stream. As such, if the Maxim DP display serializers are configured in MST mode, it is recommended to always enable all video streams that will be used at once.

Configuring the Maxim HDMI Serializer

If you are using the NVIDIA Maxim HDMI serializer driver, there are various ways to configure the driver by using Device Tree, As shown in the following example:

i2c@31e0000 {
    status = "okay";
    maxim_ser: maxim_gmsl_hdmi_ser@40 {
        compatible = "maxim,maxim_gmsl_hdmi_ser";
        reg = <0x40>;
        status = "okay";
        maxim_gmsl_hdmi_ser-pwrdn = <&tegra_main_gpio TEGRA234_MAIN_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
        ser-errb = <&tegra_main_gpio TEGRA234_MAIN_GPIO(G, 7) 0>;
        enable_rclkout = <0x1>;
      };
};

A description of each of the preceding properties:

• Required properties
  • compatible: Must be maxim,maxim_gmsl_hdmi_ser.
  • reg: I2C register address of Maxim HDMI serializer.
  • maxim_gmsl_hdmi_ser-pwrdn: GPIO pin number of the PWRDN pin. This pin is used to power up the Maxim HDMI display serializer chip.
  • ser-errb: GPIO pin number of the ERRB pin. This pin is used for error and fault reporting by the serializer chip.
• Optionals properties
  • enable_rclkout: RCLOUT signal is going as an input to camera deserializer and working as a clock source.

The Maxim HDMI display serializer does not support multiple links and by default uses the Link A of the serializer.

Configuring the TI Serializer Driver

      i2c@31e0000 { /* i2c8 */
		status = "okay";
		ti_ser: ti_fpdlink_dp_ser@18 {
			compatible = "ti,ti_fpdlink_dp_ser";
			reg = <0x18>;
			status = "okay";
			ti_fpdlink_dp_ser-pwrdn = <&tegra_main_gpio TEGRA234_MAIN_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
			dprx-link-rate = <0x0A>;
			dprx-lane-count = <0x4>;
			timings-phandle = <&mode0>;
			fpd-link-select = <0x1 0x0>;
		};

The properties of the preceding example are described as follows:

• Required properties:

  • compatible: Must be ti,ti_fpdlink_dp_ser.

  • reg: I2C address of the TI display serializer.

  • ti_fpdlink_dp_ser-pwrdn: GPIO pin number of the PWRDN pin. This pin is used to power up the TI display serializer chip.

  • timings-phandle: This property should be set as mode0 or mode1 to reflect raster or display timings used by the NVIDIA reference platforms.

  • fpd-link-select: This property is an array of two unsigned 8-bit values that represent FPDlink port IDs. First field is for link A and the second is for link B. Value 0 indicates that the link is disabled and value 1 indicates that the link is enabled. At any given time, only one link is supported.

• Optional properties:

  • dprx-link-rate: Configures the DP link rate of the serializer chip.

    The default value is 0x1E (HBR3). The possible values are:

    • 0xA (HBR)

    • 0x14 (HBR2)

    • 0x1E (HBR3)

  • dprx-lane-count: Configures the DP lane count of the serializer chip.

    The default value is 0x4. The possible values are:

    • 0x1

    • 0x2

    • 0x4

bind_partitions -b p3710-12-a01 linux DISP_SER_MODULE=TI983