NvSIPLCommon.hpp

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/*
 * Copyright (c) 2018-2022, NVIDIA CORPORATION.  All rights reserved.
 *
 * NVIDIA CORPORATION and its licensors retain all intellectual property
 * and proprietary rights in and to this software, related documentation
 * and any modifications thereto.  Any use, reproduction, disclosure or
 * distribution of this software and related documentation without an express
 * license agreement from NVIDIA CORPORATION is strictly prohibited.
 */
 
#ifndef NVSIPLCOMMON_HPP
#define NVSIPLCOMMON_HPP
 
#include <memory>
#include <math.h>
 
namespace nvsipl
{
typedef struct {
    uint16_t x0;
    uint16_t y0;
    uint16_t x1;
    uint16_t y1;
} NvSiplRect;
 
typedef uint64_t NvSiplGlobalTime;
 
typedef struct {
    int32_t x;
    int32_t y;
} NvSiplPoint;
 
typedef struct {
    float_t x;
    float_t y;
} NvSiplPointFloat;
 
#define SIPL_TRUE  (0 == 0)
 
#define SIPL_FALSE (0 == 1)
 
typedef uint32_t NvSiplBool;
 
typedef enum {
    NVSIPL_TIME_BASE_CLOCK_PTP = 0,
    NVSIPL_TIME_BASE_CLOCK_MONOTONIC,
    NVSIPL_TIME_BASE_CLOCK_USER_DEFINED,
} NvSiplTimeBase;
 
enum SIPLStatus
{
    // New status code must be added after NVSIPL_STATUS_OK and before NVSIPL_STATUS_ERROR.
 
    NVSIPL_STATUS_OK = 0,
 
    // Error codes.
    NVSIPL_STATUS_BAD_ARGUMENT,
    NVSIPL_STATUS_NOT_SUPPORTED,
    NVSIPL_STATUS_OUT_OF_MEMORY,
    NVSIPL_STATUS_RESOURCE_ERROR,
    NVSIPL_STATUS_TIMED_OUT,
    NVSIPL_STATUS_INVALID_STATE,
    NVSIPL_STATUS_EOF,
    NVSIPL_STATUS_NOT_INITIALIZED,
    NVSIPL_STATUS_FAULT_STATE,
    NVSIPL_STATUS_ERROR
};
 
enum SIPLGpioEvent
{
    NVSIPL_GPIO_EVENT_NOTHING = 0,
    NVSIPL_GPIO_EVENT_INTR,
    NVSIPL_GPIO_EVENT_ERROR_WAIT_CANCELLED,
    NVSIPL_GPIO_EVENT_ERROR_CDAC,
    NVSIPL_GPIO_EVENT_ERROR_BACKEND,
    NVSIPL_GPIO_EVENT_ERROR_UNKNOWN,
};
 
typedef struct {
    std::unique_ptr<uint8_t []> upErrorBuffer;
 
    size_t bufferSize;
 
    size_t sizeWritten;
} SIPLErrorDetails;
 
enum SIPLModuleErrorReadFlag
{
    NVSIPL_MODULE_ERROR_READ_SENSOR,
    NVSIPL_MODULE_ERROR_READ_SERIALIZER,
    NVSIPL_MODULE_ERROR_READ_ALL,
};
 
}  // namespace nvsipl
 
#endif // NVSIPLCOMMON_HPP