NvSys Structure Changes#

API Prototype Changes#

Target Changes

Backward Compatible

Platform

OS

In 7.2.3.0, the API prototype for reading ECID NvTegraSysGetFuseHashedECID() changed from 128bit to 512bit with new structure NvSysTegraECID in header file (nvsocsysapi.h).

No

NSR

SR

QNX only

Migration Path

  • Orin to Thor

Migration Release Path

6.x to 7.2

Migration Rationale

The Orin and Thor SOC use a 512-bit ECID for improved security. NvTegraSysGetFuseHashedECID() is updated to return the full 512-bit ECID instead of a truncated 128-bit value.

Steps to Migrate

Usage of the API prototype for reading ECID is described in “System ECID Information” in the NVIDIA DriveOS Developer Guide.

Fuse Accessor API Restructuring#

Target Changes

Backward Compatible

Platform

OS

  • The QNX-only declarations of NvTegraSysGetFuseODMData and the 4x32-bit NvTegraSysGetFuseHashedECID (taking four NvU32 * outputs) were removed from nvsocsysapi_qnx.h and consolidated into the cross-platform nvsocsysapi.h.

  • NvTegraSysGetFuseHashedECID now takes a single NvSysTegraECID * output argument (512-bit struct) instead of four NvU32 * pointers. Custom ability nvsys/hashed_ecid.

  • NvTegraSysGetFuseODMData (signature NvSocSysErrCode NvTegraSysGetFuseODMData(NvU32 *ODMID_0, NvU32 *ODMID_1, NvU32 *ODMInfo)) is now exposed from nvsocsysapi.h with custom ability nvsys/odm_info.

  • The NvSocFuseOPTInfo enum was reshaped: the entries TEGRA_FUSE_OPT_ODMID0 (0xCC), TEGRA_FUSE_OPT_ODMID1 (0xF0), TEGRA_FUSE_OPT_ODM_INFO (0xFF), and the four hashed-ECID entries TEGRA_FUSE_OPT_ECID_0 .. TEGRA_FUSE_OPT_ECID_3 were removed. Their data is now read via the new typed accessors above instead of through NvTegraSysGetFuseOPT_info.

  • Nine new “disable” entries were added to NvSocFuseOPTInfo for new fuse-controlled IP-block disables on T26x silicon: TEGRA_FUSE_OPT_UCF_CLUSTER_DISABLE (0x34F), TEGRA_FUSE_OPT_AUDIO_DISABLE (0x350), TEGRA_FUSE_OPT_ISP_DISABLE (0x35F), TEGRA_FUSE_OPT_VIC_DISABLE (0x3C6), TEGRA_FUSE_OPT_DISPLAY_DISABLE (0x3C9), TEGRA_FUSE_OPT_MSS_DISABLE (0x359), TEGRA_FUSE_OPT_PCIE_DISABLE (0x365), TEGRA_FUSE_OPT_MGBE_DISABLE (0x36A), TEGRA_FUSE_OPT_HWPM_DISABLE (0x9AC).

No. Source changes are required.

SR

QNX

Migration Path

  • Orin to Thor

Migration Release Path

6.5.4.2 to 7.2.5.0

Migration Rationale

ODM / hashed-ECID fuses now have dedicated typed accessors in the cross-platform nvsocsysapi.h instead of being read through the generic NvTegraSysGetFuseOPT_info enum, and the four-NvU32 ECID API is replaced by a single 512-bit struct that matches the silicon’s actual ECID width. The OPT enum was simultaneously expanded with new disable bits for T26x IP-blocks.

Steps to Migrate

  1. Replace any call to NvTegraSysGetFuseOPT_info that used TEGRA_FUSE_OPT_ODMID0 / TEGRA_FUSE_OPT_ODMID1 / TEGRA_FUSE_OPT_ODM_INFO or TEGRA_FUSE_OPT_ECID_0..3 with the new typed accessors. Compile-time signal of this break: 'TEGRA_FUSE_OPT_ODMID0' undeclared.

    // before
NvU32 odmid0 = 0U;
(void)NvTegraSysGetFuseOPT_info(TEGRA_FUSE_OPT_ODMID0, &odmid0);
NvU32 ecid0 = 0U;
(void)NvTegraSysGetFuseOPT_info(TEGRA_FUSE_OPT_ECID_0, &ecid0);

    // after
NvU32 odmid0 = 0U, odmid1 = 0U, odminfo = 0U;
(void)NvTegraSysGetFuseODMData(&odmid0, &odmid1, &odminfo);
NvSysTegraECID ecid;
(void)NvTegraSysGetFuseHashedECID(&ecid);

  2. Update any call to the QNX-only four-NvU32 hashed-ECID API to the new single-struct form declared in nvsocsysapi.h. Compile-time signal of this break: too many arguments to function 'NvTegraSysGetFuseHashedECID'.

    // before (QNX-only, four NvU32 pointers)
NvU32 e0, e1, e2, e3;
(void)NvTegraSysGetFuseHashedECID(&e0, &e1, &e2, &e3);

    // after (cross-platform, single 512-bit struct)
NvSysTegraECID ecid;
(void)NvTegraSysGetFuseHashedECID(&ecid);

  3. If your application enumerates NvSocFuseOPTInfo values, audit the switch / lookup-table for the removed ODMID / ODM_INFO / ECID_0..3 entries and add handling for the new *_DISABLE entries you care about.

Chip ID and Revision Enum Updates#

Target Changes

Backward Compatible

Platform

OS

  • The NvSocChipId enum is now exposed unconditionally. Previously TEGRA_CHIPID_TEGRA26 was gated by NV_BUILD_CONFIGURATION_EXPOSING_T26X; the gate was removed and a new value TEGRA_CHIPID_TEGRA25 (= 0x25U) was added. TEGRA_CHIPID_TEGRA26 retains the value 0x26U.

  • The NvSocRevision enum was restructured. New values TEGRA_REVISION_A00B (0x10U), TEGRA_REVISION_A00P (0x11U), TEGRA_REVISION_A01Q (0x55U), and TEGRA_REVISION_A02Q (0x69U) were added. The lower-case-suffixed names TEGRA_REVISION_A01p and TEGRA_REVISION_A02p were renamed to TEGRA_REVISION_A01P and TEGRA_REVISION_A02P (case change).

  • The numeric encoding of several existing NvSocRevision values was renumbered: TEGRA_REVISION_A02 0x55 -> 0x5A, TEGRA_REVISION_A03 0x66 -> 0x96, TEGRA_REVISION_QT 0x69 -> 0xF0, TEGRA_REVISION_SIM 0x96 -> 0xFF. Code that compared NvSocRevision against hard-coded integers must be updated.

No. Persisted data / wire values may differ.

SR

QNX

Migration Path

  • Orin to Thor

Migration Release Path

6.5.4.2 to 7.2.5.0

Migration Rationale

Drop the build-time gating around the T26x chip-id and add the previously-undeclared T25x chip-id; re-spread the chip revision codes to align with the silicon revision-table updates and to free up integer slots for new sub-revisions.

Steps to Migrate

  1. Remove any #ifdef NV_BUILD_CONFIGURATION_EXPOSING_T26X guards around references to TEGRA_CHIPID_TEGRA26; add handling for TEGRA_CHIPID_TEGRA25 where appropriate.

    // before
#if NV_BUILD_CONFIGURATION_EXPOSING_T26X
    case TEGRA_CHIPID_TEGRA26: ...
#endif

    // after
case TEGRA_CHIPID_TEGRA25: ...
case TEGRA_CHIPID_TEGRA26: ...

  2. Replace lower-case-suffixed NvSocRevision names with the upper-case form. Compile-time signal of this break: 'TEGRA_REVISION_A01p' undeclared.

    // before
if (rev == TEGRA_REVISION_A01p) { ... }
if ((uint32_t)rev == 0x96U) { /* SIM */ }

    // after
if (rev == TEGRA_REVISION_A01P) { ... }
if (rev == TEGRA_REVISION_SIM)  { /* SIM, now 0xFF */ }

  3. Audit any code that compares NvSocRevision against hard-coded integer values (rev == 0x55, rev == 0x96, etc.) and switch to the symbolic names. Several values were renumbered, so an integer comparison that used to match one revision may now silently match a different one.

L3 Cache Information API Removal#

Target Changes

Backward Compatible

Platform

OS

The NvTegraSysGetL3cacheInfo function and the conditional #include "qnx/tegra_l3_cache.h" it depended on were removed from nvsocsysapi.h. The symbol was previously gated by ((NV_IS_SAFETY == 0) && defined(__QNX__)) so it was only ever visible on non-safety QNX builds; safety builds were unaffected.

No. Source changes are required.

SR

QNX

Migration Path

  • Orin to Thor

Migration Release Path

6.5.4.2 to 7.2.5.0

Migration Rationale

The L3-cache info accessor is no longer part of the public cross-platform API surface.

Steps to Migrate

  1. Remove any call to NvTegraSysGetL3cacheInfo. There is no public replacement; consult internal L3-cache facilities outside the public SDK headers if the data is still required. Compile-time signal of this break: implicit declaration of function 'NvTegraSysGetL3cacheInfo'.

    // before
struct tegra_l3_ioctl_data l3;
(void)NvTegraSysGetL3cacheInfo(&l3);

    // after
// no replacement; remove the call (or use a non-public l3-cache path
// outside the public SDK headers).