Display Device Tree#
This topic applies only to QNX builds running on Orin platforms.
Display Device Tree#
The NvDisplay driver uses the following device tree nodes and properties. Properties customizable are marked accordingly for each property used. Nodes used in NvDisplay drivers for Linux are as follows.
NvDisplay#
nvdisplay node contains configuration parameters for initializing the NvDisplay driver.
nvdisplay: display@8808c00000 {
compatible = "nvidia,tegra264-display";
power-domains = <&bpmp TEGRA264_POWER_DOMAIN_DISP>;
nvidia,num-dpaux-instance = <0x00000004>;
nvidia,bpmp = <&bpmp>;
reg-names = "nvdisplay", "dpaux0", "hdacodec", "mipical", "vdisp";
reg = <0x88 0x8c00000 0x00 0x1fffff>,
<0x88 0x9680000 0x00 0x7ffff>,
<0x88 0x9101000 0x00 0xfff>,
<0x81 0x89840000 0x00 0xffff>,
<0x88 0x8d00000 0x00 0x00010000>;
interrupt-names = "nvdisplay", "dpaux0", "dpaux1", "dpaux2", "dpaux3", "hdacodec", "vdisp";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&bpmp TEGRA264_CLK_HUB>,
<&bpmp TEGRA264_CLK_DISP>,
<&bpmp TEGRA264_CLK_RG0_DIV>,
<&bpmp TEGRA264_CLK_RG1_DIV>,
<&bpmp TEGRA264_CLK_RG2_DIV>,
<&bpmp TEGRA264_CLK_RG3_DIV>,
<&bpmp TEGRA264_CLK_RG4_DIV>,
<&bpmp TEGRA264_CLK_RG5_DIV>,
<&bpmp TEGRA264_CLK_RG6_DIV>,
<&bpmp TEGRA264_CLK_RG7_DIV>,
<&bpmp TEGRA264_CLK_FUSE>,
<&bpmp TEGRA264_CLK_SPPLL0_CLKOUT1A>,
<&bpmp TEGRA264_CLK_SPPLL0_CLKOUT2A>,
<&bpmp TEGRA264_CLK_SPPLL0_CLKOUT270>,
<&bpmp TEGRA264_CLK_SPPLL1_CLKOUT270>,
<&bpmp TEGRA264_CLK_SPPLL0_CLKOUT100>,
<&bpmp TEGRA264_CLK_SPPLL1_CLKOUT100>,
<&bpmp TEGRA264_CLK_VPLL0>,
<&bpmp TEGRA264_CLK_VPLL1>,
<&bpmp TEGRA264_CLK_VPLL2>,
<&bpmp TEGRA264_CLK_VPLL3>,
<&bpmp TEGRA264_CLK_VPLL4>,
<&bpmp TEGRA264_CLK_VPLL5>,
<&bpmp TEGRA264_CLK_VPLL6>,
<&bpmp TEGRA264_CLK_VPLL7>,
<&bpmp TEGRA264_CLK_RG0>,
<&bpmp TEGRA264_CLK_RG1>,
<&bpmp TEGRA264_CLK_RG2>,
<&bpmp TEGRA264_CLK_RG3>,
<&bpmp TEGRA264_CLK_RG4>,
<&bpmp TEGRA264_CLK_RG5>,
<&bpmp TEGRA264_CLK_RG6>,
<&bpmp TEGRA264_CLK_RG7>,
<&bpmp TEGRA264_CLK_DISPPLL>,
<&bpmp TEGRA264_CLK_PRE_SOR0>,
<&bpmp TEGRA264_CLK_PRE_SOR1>,
<&bpmp TEGRA264_CLK_PRE_SOR2>,
<&bpmp TEGRA264_CLK_PRE_SOR3>,
<&bpmp TEGRA264_CLK_DP_LINKA_REF>,
<&bpmp TEGRA264_CLK_DP_LINKB_REF>,
<&bpmp TEGRA264_CLK_DP_LINKC_REF>,
<&bpmp TEGRA264_CLK_DP_LINKD_REF>,
<&bpmp TEGRA264_CLK_SOR_LINKA_INPUT>,
<&bpmp TEGRA264_CLK_SOR_LINKB_INPUT>,
<&bpmp TEGRA264_CLK_SOR_LINKC_INPUT>,
<&bpmp TEGRA264_CLK_SOR_LINKD_INPUT>,
<&bpmp TEGRA264_CLK_SOR_LINKA_AFIFO>,
<&bpmp TEGRA264_CLK_SOR_LINKB_AFIFO>,
<&bpmp TEGRA264_CLK_SOR_LINKC_AFIFO>,
<&bpmp TEGRA264_CLK_SOR_LINKD_AFIFO>,
<&bpmp TEGRA264_CLK_SOR0>,
<&bpmp TEGRA264_CLK_SOR1>,
<&bpmp TEGRA264_CLK_SOR2>,
<&bpmp TEGRA264_CLK_SOR3>,
<&bpmp TEGRA264_CLK_LINKA_SYM>,
<&bpmp TEGRA264_CLK_LINKB_SYM>,
<&bpmp TEGRA264_CLK_LINKC_SYM>,
<&bpmp TEGRA264_CLK_LINKD_SYM>,
<&bpmp TEGRA264_CLK_SOR0_PAD>,
<&bpmp TEGRA264_CLK_SOR1_PAD>,
<&bpmp TEGRA264_CLK_SOR2_PAD>,
<&bpmp TEGRA264_CLK_SOR3_PAD>,
<&bpmp TEGRA264_CLK_SF0>,
<&bpmp TEGRA264_CLK_SF1>,
<&bpmp TEGRA264_CLK_SF2>,
<&bpmp TEGRA264_CLK_SF3>,
<&bpmp TEGRA264_CLK_SF4>,
<&bpmp TEGRA264_CLK_SF5>,
<&bpmp TEGRA264_CLK_SF6>,
<&bpmp TEGRA264_CLK_SF7>,
<&bpmp TEGRA264_CLK_SOR0_PLL_REF>,
<&bpmp TEGRA264_CLK_SOR1_PLL_REF>,
<&bpmp TEGRA264_CLK_SOR2_PLL_REF>,
<&bpmp TEGRA264_CLK_SOR3_PLL_REF>,
<&bpmp TEGRA264_CLK_SOR0_REF>,
<&bpmp TEGRA264_CLK_SOR1_REF>,
<&bpmp TEGRA264_CLK_SOR2_REF>,
<&bpmp TEGRA264_CLK_SOR3_REF>,
<&bpmp TEGRA264_CLK_OSC>,
<&bpmp TEGRA264_CLK_DSC>,
<&bpmp TEGRA264_CLK_MAUD>,
<&bpmp TEGRA264_CLK_AZA_2XBIT>,
<&bpmp TEGRA264_CLK_DISP_ROOT>,
<&bpmp TEGRA264_CLK_VPLLX_SOR0_MUXED>,
<&bpmp TEGRA264_CLK_VPLLX_SOR1_MUXED>,
<&bpmp TEGRA264_CLK_VPLLX_SOR2_MUXED>,
<&bpmp TEGRA264_CLK_VPLLX_SOR3_MUXED>,
<&bpmp TEGRA264_CLK_SF0_SOR>,
<&bpmp TEGRA264_CLK_SF1_SOR>,
<&bpmp TEGRA264_CLK_SF2_SOR>,
<&bpmp TEGRA264_CLK_SF3_SOR>,
<&bpmp TEGRA264_CLK_SF4_SOR>,
<&bpmp TEGRA264_CLK_SF5_SOR>,
<&bpmp TEGRA264_CLK_SF6_SOR>,
<&bpmp TEGRA264_CLK_SF7_SOR>,
<&bpmp TEGRA264_CLK_DPAUX>,
<&bpmp TEGRA264_CLK_EMC>;
clock-names = "nvdisplayhub_clk",
"nvdisplay_disp_clk",
"nvdisplay_p0_clk",
"nvdisplay_p1_clk",
"nvdisplay_p2_clk",
"nvdisplay_p3_clk",
"nvdisplay_p4_clk",
"nvdisplay_p5_clk",
"nvdisplay_p6_clk",
"nvdisplay_p7_clk",
"fuse_clk",
"sppll0_clkouta_clk",
"sppll0_clkoutb_clk",
"sppll0_clkoutpn_clk",
"sppll1_clkoutpn_clk",
"sppll0_div27_clk",
"sppll1_div27_clk",
"vpll0_clk",
"vpll1_clk",
"vpll2_clk",
"vpll3_clk",
"vpll4_clk",
"vpll5_clk",
"vpll6_clk",
"vpll7_clk",
"rg0_clk",
"rg1_clk",
"rg2_clk",
"rg3_clk",
"rg4_clk",
"rg5_clk",
"rg6_clk",
"rg7_clk",
"disppll_clk",
"pre_sor0_clk",
"pre_sor1_clk",
"pre_sor2_clk",
"pre_sor3_clk",
"dp_link_ref_clk",
"dp_linkb_ref_clk",
"dp_linkc_ref_clk",
"dp_linkd_ref_clk",
"sor_linka_input_clk",
"sor_linkb_input_clk",
"sor_linkc_input_clk",
"sor_linkd_input_clk",
"sor_linka_afifo_clk",
"sor_linkb_afifo_clk",
"sor_linkc_afifo_clk",
"sor_linkd_afifo_clk",
"sor0_clk",
"sor1_clk",
"sor2_clk",
"sor3_clk",
"sor_pad_input_clk",
"sor_padb_input_clk",
"sor_padc_input_clk",
"sor_padd_input_clk",
"sor0_pad_clk",
"sor1_pad_clk",
"sor2_pad_clk",
"sor3_pad_clk",
"sf0_clk",
"sf1_clk",
"sf2_clk",
"sf3_clk",
"sf4_clk",
"sf5_clk",
"sf6_clk",
"sf7_clk",
"sor0_ref_pll_clk",
"sor1_ref_pll_clk",
"sor2_ref_pll_clk",
"sor3_ref_pll_clk",
"sor0_ref_clk",
"sor1_ref_clk",
"sor2_ref_clk",
"sor3_ref_clk",
"osc_clk",
"dsc_clk",
"maud_clk",
"aza_2xbit_clk",
"disp_root",
"vpllx_sor0_muxed_clk",
"vpllx_sor1_muxed_clk",
"vpllx_sor2_muxed_clk",
"vpllx_sor3_muxed_clk",
"sf0_sor_clk",
"sf1_sor_clk",
"sf2_sor_clk",
"sf3_sor_clk",
"sf4_sor_clk",
"sf5_sor_clk",
"sf6_sor_clk",
"sf7_sor_clk",
"dpaux0_clk",
"emc_clk";
nvidia,disp-sw-soc-chip-id = <0x2650>;
resets = <&bpmp TEGRA264_RESET_DPAUX>,
<&bpmp TEGRA264_RESET_HDACODEC>;
reset-names = "dpaux0_reset", "hdacodec_reset";
interconnects = <&mc TEGRA264_MEMORY_CLIENT_DISPR &emc>;
interconnect-names = "read-1";
status = "disabled";
iommus = <&smmu3_mmu 0x900>;
non-coherent;
nvdisplay-niso {
compatible = "nvidia,tegra264-display-niso";
iommus = <&smmu3_mmu 0x901>;
dma-coherent;
status = "disabled";
};
};
compatible
Description: - compatible contains the unique string to identify the external NvDisplay DT node.
Customizable: No
Optional: No
Value: ” nvidia,tegra264-display”
power-domains
Description: - power-domains identifies the power domain display belongs to.
Customizable: No
Optional: No
Value: <&bpmp TEGRA264_POWER_DOMAIN_DISP>
nvidia,num-dpaux-instance
Description: - num-dpaux-instance specifies the number of DPAUX pads on the underlying platform.
Customizable: No
Optional: No
Value: <0x00000004>
reg-names
Description: - reg-names mentions all of the MMIO device apertures that the display driver needs access to.
Customizable: No
Optional: No
Value:
nvdisplay
dpaux0
hdacodec
mipical
vdisp
reg
Description: - Physical base address and length of the controller’s registers
Customizable: No
Optional: No
Value: Tuple in the form of address and length/size that describes the address range. Must contain an entry for each register entry mentioned in the reg field:
0x88 0x8c00000 0x00 0x1fffff
0x88 0x9680000 0x00 0x7ffff
0x88 0x9101000 0x00 0xfff
0x81 0x89840000 0x00 0xffff
0x88 0x8d00000 0x00 0x00010000
interrupt-names
Description: - Mentions the type of interrupts supported by NvDisplay node.
Customizable: No
Optional: No
Value: Must contain the following entries:
nvdisplay
dpaux0
hdacodec
dpaux1
dpaux2
dpaux3
vdisp
interrupts
Description: interrupts holds the IRQ number and IRQ type connected to NvDisplay.
Customizable: No
Optional: No
Value: Must contain an entry for each entry in interrupt-names.
0 256 4
0 247 4
0 248 4
0 249 4
0 250 4
0 252 4
0 257 4
nvidia,bpmp
Description: BPMP device, needed for NvDisplay
Customizable: No
Optional: No
Value: bpmp
clocks
Description: clocks holds the type of clock IDs supported by NvDisplay.
Customizable: No
Optional: No
Value:
<&bpmp TEGRA264_CLK_HUB>,
<&bpmp TEGRA264_CLK_DISP>,
<&bpmp TEGRA264_CLK_RG0_DIV>,
<&bpmp TEGRA264_CLK_RG1_DIV>,
<&bpmp TEGRA264_CLK_RG2_DIV>,
<&bpmp TEGRA264_CLK_RG3_DIV>,
<&bpmp TEGRA264_CLK_RG4_DIV>,
<&bpmp TEGRA264_CLK_RG5_DIV>,
<&bpmp TEGRA264_CLK_RG6_DIV>,
<&bpmp TEGRA264_CLK_RG7_DIV>,
<&bpmp TEGRA264_CLK_FUSE>,
<&bpmp TEGRA264_CLK_SPPLL0_CLKOUT1A>,
<&bpmp TEGRA264_CLK_SPPLL0_CLKOUT2A>,
<&bpmp TEGRA264_CLK_SPPLL0_CLKOUT270>,
<&bpmp TEGRA264_CLK_SPPLL1_CLKOUT270>,
<&bpmp TEGRA264_CLK_SPPLL0_CLKOUT100>,
<&bpmp TEGRA264_CLK_SPPLL1_CLKOUT100>,
<&bpmp TEGRA264_CLK_VPLL0>,
<&bpmp TEGRA264_CLK_VPLL1>,
<&bpmp TEGRA264_CLK_VPLL2>,
<&bpmp TEGRA264_CLK_VPLL3>,
<&bpmp TEGRA264_CLK_VPLL4>,
<&bpmp TEGRA264_CLK_VPLL5>,
<&bpmp TEGRA264_CLK_VPLL6>,
<&bpmp TEGRA264_CLK_VPLL7>,
<&bpmp TEGRA264_CLK_RG0>,
<&bpmp TEGRA264_CLK_RG1>,
<&bpmp TEGRA264_CLK_RG2>,
<&bpmp TEGRA264_CLK_RG3>,
<&bpmp TEGRA264_CLK_RG4>,
<&bpmp TEGRA264_CLK_RG5>,
<&bpmp TEGRA264_CLK_RG6>,
<&bpmp TEGRA264_CLK_RG7>,
<&bpmp TEGRA264_CLK_DISPPLL>,
<&bpmp TEGRA264_CLK_PRE_SOR0>,
<&bpmp TEGRA264_CLK_PRE_SOR1>,
<&bpmp TEGRA264_CLK_PRE_SOR2>,
<&bpmp TEGRA264_CLK_PRE_SOR3>,
<&bpmp TEGRA264_CLK_DP_LINKA_REF>,
<&bpmp TEGRA264_CLK_DP_LINKB_REF>,
<&bpmp TEGRA264_CLK_DP_LINKC_REF>,
<&bpmp TEGRA264_CLK_DP_LINKD_REF>,
<&bpmp TEGRA264_CLK_SOR_LINKA_INPUT>,
<&bpmp TEGRA264_CLK_SOR_LINKB_INPUT>,
<&bpmp TEGRA264_CLK_SOR_LINKC_INPUT>,
<&bpmp TEGRA264_CLK_SOR_LINKD_INPUT>,
<&bpmp TEGRA264_CLK_SOR_LINKA_AFIFO>,
<&bpmp TEGRA264_CLK_SOR_LINKB_AFIFO>,
<&bpmp TEGRA264_CLK_SOR_LINKC_AFIFO>,
<&bpmp TEGRA264_CLK_SOR_LINKD_AFIFO>,
<&bpmp TEGRA264_CLK_SOR0>,
<&bpmp TEGRA264_CLK_SOR1>,
<&bpmp TEGRA264_CLK_SOR2>,
<&bpmp TEGRA264_CLK_SOR3>,
<&bpmp TEGRA264_CLK_LINKA_SYM>,
<&bpmp TEGRA264_CLK_LINKB_SYM>,
<&bpmp TEGRA264_CLK_LINKC_SYM>,
<&bpmp TEGRA264_CLK_LINKD_SYM>,
<&bpmp TEGRA264_CLK_SOR0_PAD>,
<&bpmp TEGRA264_CLK_SOR1_PAD>,
<&bpmp TEGRA264_CLK_SOR2_PAD>,
<&bpmp TEGRA264_CLK_SOR3_PAD>,
<&bpmp TEGRA264_CLK_SF0>,
<&bpmp TEGRA264_CLK_SF1>,
<&bpmp TEGRA264_CLK_SF2>,
<&bpmp TEGRA264_CLK_SF3>,
<&bpmp TEGRA264_CLK_SF4>,
<&bpmp TEGRA264_CLK_SF5>,
<&bpmp TEGRA264_CLK_SF6>,
<&bpmp TEGRA264_CLK_SF7>,
<&bpmp TEGRA264_CLK_SOR0_PLL_REF>,
<&bpmp TEGRA264_CLK_SOR1_PLL_REF>,
<&bpmp TEGRA264_CLK_SOR2_PLL_REF>,
<&bpmp TEGRA264_CLK_SOR3_PLL_REF>,
<&bpmp TEGRA264_CLK_SOR0_REF>,
<&bpmp TEGRA264_CLK_SOR1_REF>,
<&bpmp TEGRA264_CLK_SOR2_REF>,
<&bpmp TEGRA264_CLK_SOR3_REF>,
<&bpmp TEGRA264_CLK_OSC>,
<&bpmp TEGRA264_CLK_DSC>,
<&bpmp TEGRA264_CLK_MAUD>,
<&bpmp TEGRA264_CLK_AZA_2XBIT>,
<&bpmp TEGRA264_CLK_DISP_ROOT>,
<&bpmp TEGRA264_CLK_VPLLX_SOR0_MUXED>,
<&bpmp TEGRA264_CLK_VPLLX_SOR1_MUXED>,
<&bpmp TEGRA264_CLK_VPLLX_SOR2_MUXED>,
<&bpmp TEGRA264_CLK_VPLLX_SOR3_MUXED>,
<&bpmp TEGRA264_CLK_SF0_SOR>,
<&bpmp TEGRA264_CLK_SF1_SOR>,
<&bpmp TEGRA264_CLK_SF2_SOR>,
<&bpmp TEGRA264_CLK_SF3_SOR>,
<&bpmp TEGRA264_CLK_SF4_SOR>,
<&bpmp TEGRA264_CLK_SF5_SOR>,
<&bpmp TEGRA264_CLK_SF6_SOR>,
<&bpmp TEGRA264_CLK_SF7_SOR>,
<&bpmp TEGRA264_CLK_DPAUX>;
clock-names
Description: List of clock input name strings sorted in the same order as the clocks property. Consumer drivers use clock-names to match clock input names with clocks specifiers.
Customizable: No
Optional: No
Value:
“nvdisplayhub_clk”,“nvdisplay_disp_clk”,“nvdisplay_p0_clk”,“nvdisplay_p1_clk”,“nvdisplay_p2_clk”,“nvdisplay_p3_clk”,“nvdisplay_p4_clk”,
“nvdisplay_p5_clk”,“nvdisplay_p6_clk”,“nvdisplay_p7_clk”,“fuse_clk”,“sppll0_clkouta_clk”,“sppll0_clkoutb_clk”,“sppll0_clkoutpn_clk”,
“sppll1_clkoutpn_clk”,“sppll0_div27_clk”,“sppll1_div27_clk”,“vpll0_clk”,“vpll1_clk”,“vpll2_clk”,“vpll3_clk”,“vpll4_clk”,“vpll5_clk”,
“vpll6_clk”,“vpll7_clk”,“rg0_clk”,“rg1_clk”,“rg2_clk”,“rg3_clk”,“rg4_clk”,“rg5_clk”,“rg6_clk”,“rg7_clk”,“disppll_clk”,“pre_sor0_clk”,
“pre_sor1_clk”,“pre_sor2_clk”,“pre_sor3_clk”,“dp_link_ref_clk”,“dp_linkb_ref_clk”,“dp_linkc_ref_clk”,“dp_linkd_ref_clk”,
“sor_linka_input_clk”,“sor_linkb_input_clk”,“sor_linkc_input_clk”,“sor_linkd_input_clk”,“sor_linka_afifo_clk”,“sor_linkb_afifo_clk”,
“sor_linkc_afifo_clk”,“sor_linkd_afifo_clk”,“sor0_clk”,“sor1_clk”,“sor2_clk”,“sor3_clk”,“sor_pad_input_clk”,“sor_padb_input_clk”,
“sor_padc_input_clk”,“sor_padd_input_clk”,“sor0_pad_clk”,“sor1_pad_clk”,“sor2_pad_clk”,“sor3_pad_clk”,“sf0_clk”,“sf1_clk”,
“sf2_clk”,“sf3_clk”,“sf4_clk”,“sf5_clk”,“sf6_clk”,“sf7_clk”,“sor0_ref_pll_clk”,“sor1_ref_pll_clk”,“sor2_ref_pll_clk”,
“sor3_ref_pll_clk”,“sor0_ref_clk”,“sor1_ref_clk”,“sor2_ref_clk”,“sor3_ref_clk”,“osc_clk”,“dsc_clk”,“maud_clk”,
“aza_2xbit_clk”,“disp_root”,“vpllx_sor0_muxed_clk”,“vpllx_sor1_muxed_clk”,“vpllx_sor2_muxed_clk”,
“vpllx_sor3_muxed_clk”,“sf0_sor_clk”,“sf1_sor_clk”,“sf2_sor_clk”,“sf3_sor_clk”,“sf4_sor_clk”,“sf5_sor_clk”,“sf6_sor_clk”,
“sf7_sor_clk”,“dpaux0_clk”;
resets
Description: List of phandle and reset specifier pairs: one pair for each reset signal that affects the device or that the device manages.
Customizable: No
Optional: No
Value:
TEGRA264_RESET_DPAUX
TEGRA264_RESET_HDACODEC
reset-names
Description: The name of the resets mentioned in the resets field.
Customizable: No
Optional: No
Value: Must contain an entry for each value in the “resets” field:
dpaux0_reset
hdacodec_reset
status
Description: Holds the status of NvDisplay.
Customizable: No
Optional: No
Value: “okay” or “disabled”
nvidia,disp-sw-soc-chip-id
Description: Mentions the SoC software Chip ID.
Customizable: No
Optional: No
Value: 0x2650
interconnects
Description: Specifies the bandwidth of the clients used by NvDisplay. This is only if TEGRA_IOMMU_DT_VERSION is greater or equal to DT_VERSION_2. Not used on AV+L or AV+Q.
Customizable: No
Optional: No
Value:
TEGRA264_MEMORY_CLIENT_APEDMAR
TEGRA264_MEMORY_CLIENT_APEDMAW
interconnect-names
Description: Mentions the names of the interconnects used by NvDisplay. This is only if TEGRA_IOMMU_DT_VERSION is greater or equal to DT_VERSION_2.
Customizable: No
Optional: No
Value: Must contain an entry for each value in interconnects field.
dma-mem
write
iommus
Description: Mentions the name of the IOMMU used by NvDisplay for ISO traffic.
Customizable: No
Optional: No
Value:
TEGRA_SID_DISP_NISO
non-coherent
Description: Present because NvDisplay ISO accesses to DRAM are non-coherent.
Customizable: No
Optional: No
Value: N/A
nvdisplay-niso node#
Contains details about the IOMMU instance used by NvDisplay for NISO memory accesses.
nvdisplay-niso {
compatible = "nvidia,tegra264-display-niso";
Note:
iommus = <&smmu3_mmu 0x901>;
dma-coherent;
};
compatible
Description: - compatible contains the unique string to identify the external NvDisplay-NISO DT node.
Customizable: No
Optional: No
Value:
nvidia,tegra264-display-niso
iommus
Description: Mentions the name of the IOMMU used by the NvDisplay-NISO node.
Customizable: No
Optional: No
Value:
TEGRA_SID_DISP_NISO
dma-coherent
Description: Present because NvDisplay NISO memory accesses are DMA-coherent.
Customizable: No
Optional: No
Value: N/A
Dpys, Heads, and Windows#
Head-to-Window Assignment#
Display heads and windows are configured using the head-id and window-id properties in the Device Tree.
Each window and head is defined as a child node:
Window nodes are named
window-Xand include:window-id: Must match the X inwindow-X.head-id: Indicates which head the window is assigned to.
Head nodes are named
head-X.
Constraints#
The number of child nodes in
headsandwindowsmust not exceed the hardware-supported limits.A window must not be assigned to more than one head.
At least one window must be assigned to at least one head.
Culling Behavior#
If a head has no windows assigned, the display driver disables (culls) that head and all heads with higher IDs.
For example, if the hardware supports three heads and windows are assigned only to head-0 and head-2 (skipping head-1), then both head-1 and head-2 are culled.
Per-Head Color Properties#
Each head can optionally include a color-properties node that specifies the color format of its output. If this node is omitted, NvDisplay defaults to RGB444, full-range, and sRGB gamma-encoded output.
The color-properties node currently supports one field:
output-color-format: Specifies the output pixel format. Supported values are:RGB444: Outputs RGB pixels with full color range, encoded with the sRGB gamma function. This is the default format whencolor-propertiesis not specified.YUV422: Outputs YUV pixels with full color range, encoded with the Rec709 gamma function.
Example Device Tree Snippet#
The following example configures three display heads, each with associated windows and color format settings:
display@8808c00000 { dpys { dpy-0 { hw-head-id = <0>; timing-id = <0>; connector-id = <0>; }; dpy-1 { hw-head-id = <1>; timing-id = <0>; connector-id = <1>; }; dpy-2 { hw-head-id = <2>; timing-id = <0>; connector-id = <2>; }; }; heads { head-0 { hw-head-id = <0>; color-properties { output-color-format = "RGB444"; }; }; head-1 { hw-head-id = <1>; color-properties { output-color-format = "RGB444"; }; }; head-2 { hw-head-id = <2>; color-properties { output-color-format = "RGB444"; }; }; }; windows { window-0 { window-id = <0>; head-id = <0>; }; window-1 { window-id = <1>; head-id = <0>; }; window-2 { window-id = <2>; head-id = <1>; }; window-3 { window-id = <3>; head-id = <1>; }; window-4 { window-id = <4>; head-id = <2>; }; window-5 { window-id = <5>; head-id = <2>; }; }; }; };
This example assigns Windows (2N) and (2N + 1) to Head N: one even-numbered and one odd-numbered. This results in a total of six windows, evenly distributed across three heads.
For mixed connector support and more details on the dpy and head configuration, refer to NvDisplay Mixed Connector.
Static IMP#
Starting from 7.0.2.0, NvDisplay customers must enable static IMP. To enable static IMP, you must program certain IMP settings in BCT and Device Tree files. Use the host side tool LAPTSA-IMP to generate this DT fragment.
static-imp-data {
/* Window and cursor pool config */
window-pool-config = <0x227 0x227 0x227 0x227>;
cursor-pool-config = <0x1f 0x1f>;
/* Window and cursor drain meter config */
window-drain-meter-config = <0x20 0x20 0x20 0x20>;
cursor-drain-meter-config = <0x3 0x3>;
/* Window and cursor fetch meter config */
window-fetch-meter-config = <0xf 0xf 0xf 0xf>;
cursor-fetch-meter-config = <0x2 0x2>;
/* Delay before a START_FETCH command is sent to IsoHub */
start-fetch-delay-us = <0x1a8 0x1a8>;
/* Elv start value */
elv-start = <0x4 0x4>;
/* Clock Frequencies */
hub-clock-khz = <82300>;
disp-clock-khz = <311862>;
};
};
window-pool-config
Description: Specifies the window pool config.
Customizable: Yes
Optional: No
Value: Ex: <0x227 0x227 0x227 0x227>
cursor-pool-config
Description: Specifies the cursor pool config.
Customizable: Yes
Optional: No
Value: Ex: <0x1f 0x1f>
window-drain-meter-config
Description: Specifies the window drain meter config.
Customizable: Yes
Optional: No
Value: For example: <0x20 0x20 0x20 0x20>
cursor-drain-meter-config
Description: Specifies the cursor drain meter config.
Customizable: Yes
Optional: No
Value: For example: <0x3 0x3>
window-fetch-meter-config
Description: Specifies the window fetch meter config.
Customizable: Yes
Optional: No
Value: For example: <0xf 0xf 0xf 0xf>
cursor-fetch-meter-config
Description: Specifies the cursor fetch meter config.
Customizable: Yes
Optional: No
Value: For example: <0x2 0x2>
start-fetch-delay-us
Description: Specifies the delay before a START_FETCH command is sent to IsoHub.
Customizable: Yes
Optional: No
Value: For example: <0x1a8 0x1a8>
elv-start
Description: Specifies the Elv start value.
Customizable: Yes
Optional: No
Value: For example: <0x4 0x4>
hub-clock-khz
Description: Specifies the IsoHub clock frequency in KHz.
Customizable: Yes
Optional: No
Value: For example: <82300>
disp-clock-khz
Description: Specifies the display clock frequency in KHz.
Customizable: Yes
Optional: No
Value: For example: <311862>
Serializer#
Configuring the Serializer Driver
To use the NVIDIA reference Maxim serializer driver, There are various ways to configure the driver by using device tree node and its properties. Refer to NvDisp SerDes
Configuring Video Timings
For both SST and MST mode, the mode timings that are used for each stream must be configured in Device Tree. Only one mode timing can be specified at a time for each video stream. The timings that are exposed in the EDIDs of the serializer and the panels connected to the downstream deserializer are completely ignored.
An example Device Tree fragment is shown below. In this example, a standard 1920x1080 at 60 Hz timing is specified for the video stream:
{
display@8808c00000 {
display-modes {
mode-0 {
timing-id = <0>;
clock-frequency-khz = <148500>;
hactive = <1920>;
vactive = <1080>;
hfront-porch = <88>;
hback-porch = <148>;
hsync-len = <44>;
vfront-porch = <4>;
vback-porch = <36>;
vsync-len = <5>;
rrx1k = <60000>;
pps-data = [
11 00 00 89 30 80 04 38
07 80 04 38 03 c0 03 c0
02 00 03 58 00 20 73 3e
00 0d 00 0f 00 1d 00 0e
18 00 10 f0 03 0c 20 00
06 0b 0b 33 0e 1c 2a 38
46 54 62 69 70 77 79 7b
7d 7e 01 02 01 00 09 40
09 be 19 fc 19 fa 19 f8
1a 38 1a 78 22 b6 2a b6
2a f6 2a f4 43 34 63 74
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 ];
};
};
};
};
display-modes
Used to describe which timings are used for each stream.
mode0
Each mode node contains the actual mode timing parameters that are used for a given video stream.
clock-frequency-khz
Description: Specifies the pixel clock frequency in KHz. The minimum PCLK supported is 25 MHz.
Customizable: Yes
Optional: No
Value: For example: <148500>
hactive
Description: Horizontal active pixels.
Customizable: Yes
Optional: No
Value: For example: <1920>
vactive
Description: Vertical active pixels.
Customizable: Yes
Optional: No
Value: For example: <1080>
hfront-porch
Description: Horizontal front porch.
Customizable: Yes
Optional: No
Value: For example: <88>
hback-porch
Description: Horizontal back porch.
Customizable: Yes
Optional: No
Value: For example: <148>
hsync-len
Description: Horizontal sync width.
Customizable: Yes
Optional: No
Value: For example: <44>
vfront-porch
Description: Vertical front porch.
Customizable: Yes
Optional: No
Value: For example: <4>
hback-porch
Description: Horizontal back porch.
Customizable: Yes
Optional: No
Value: Ex: <36>
vsync-len
Description: Vertical sync width.
Customizable: Yes
Optional: No
Value: Ex: <5>
rrx1k
Description: Refresh rates in units of 0.001Hz.
Customizable: Yes
Optional: No
Value: For example: <60000>
pps-data
Description: All 128B of the DSC PPS.
Customizable: Yes
Optional: Yes
Value: This property must be specified if DSC is enabled for the given timing. For example:
[
11 00 00 89 30 80 04 38
07 80 04 38 03 c0 03 c0
02 00 03 58 00 20 73 3e
00 0d 00 0f 00 1d 00 0e
18 00 10 f0 03 0c 20 00
06 0b 0b 33 0e 1c 2a 38
46 54 62 69 70 77 79 7b
7d 7e 01 02 01 00 09 40
09 be 19 fc 19 fa 19 f8
1a 38 1a 78 22 b6 2a b6
2a f6 2a f4 43 34 63 74
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 ]
DCB Tool
DCB tool is packaged in the following path:
$(SDK_TOOLS_DIR)/dcb_tool/dcb_tool
If you want to modify the DCB blob in DT, refer to the DCB documentation at:
$(SDK_TOOLS_DIR)/dcb_tool/readme.txt