NVIDIA DriveOS Linux NSR SDK API Reference
7.0.3.0 Release
nvmisc.h
Go to the documentation of this file.
1  /***************************************************************************\
2 |* *|
3 |* Copyright 1993-2015 NVIDIA, Corporation. All rights reserved. *|
4 |* *|
5 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6 |* international laws. NVIDIA, Corp. of Sunnyvale, California owns *|
7 |* copyrights, patents, and has design patents pending on the design *|
8 |* and interface of the NV chips. Users and possessors of this *|
9 |* source code are hereby granted a nonexclusive, royalty-free copy- *|
10 |* right and design patent license to use this code in individual *|
11 |* and commercial software. *|
12 |* *|
13 |* Any use of this source code must include, in the user documenta- *|
14 |* tion and internal comments to the code, notices to the end user *|
15 |* as follows: *|
16 |* *|
17 |* Copyright 1993-2015 NVIDIA, Corporation. NVIDIA has design *|
18 |* patents and patents pending in the U.S. and foreign countries. *|
19 |* *|
20 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
21 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITH- *|
22 |* OUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPORATION *|
23 |* DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, INCLUD- *|
24 |* ING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *|
25 |* PARTICULAR PURPOSE. IN NO EVENT SHALL NVIDIA, CORPORATION BE *|
26 |* LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL *|
27 |* DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, *|
28 |* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR *|
29 |* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE *|
30 |* USE OR PERFORMANCE OF THIS SOURCE CODE. *|
31 |* *|
32 |* RESTRICTED RIGHTS LEGEND: Use, duplication, or disclosure by the *|
33 |* Government is subject to restrictions as set forth in subpara- *|
34 |* graph (c) (1) (ii) of the Rights in Technical Data and Computer *|
35 |* Software clause at DFARS 52.227-7013 and in similar clauses in *|
36 |* the FAR and NASA FAR Supplement. *|
37 |* *|
38  \***************************************************************************/
39 
40 /*
41  * nvmisc.h
42  */
43 #ifndef __NV_MISC_H
44 #define __NV_MISC_H
45 
46 #ifdef __cplusplus
47 extern "C" {
48 #endif //__cplusplus
49 
50 #include "nvtypes.h"
51 
52 #if !defined(NVIDIA_UNDEF_LEGACY_BIT_MACROS)
53 //
54 // Miscellaneous macros useful for bit field manipulations
55 //
56 #define BIT(b) (1<<(b))
57 #define BIT32(b) ((NvU32)1<<(b))
58 #define BIT64(b) ((NvU64)1<<(b))
59 
60 #endif
61 
62 //
63 // It is recommended to use the following bit macros to avoid macro name
64 // collisions with other src code bases.
65 //
66 #define NVBIT(b) (1<<(b))
67 #define NVBIT32(b) ((NvU32)1<<(b))
68 #define NVBIT64(b) ((NvU64)1<<(b))
69 
70 // Index of the 'on' bit (assuming that there is only one).
71 // Even if multiple bits are 'on', result is in range of 0-31.
72 #define BIT_IDX_32(n) \
73  ((((n) & 0xFFFF0000)? 0x10: 0) | \
74  (((n) & 0xFF00FF00)? 0x08: 0) | \
75  (((n) & 0xF0F0F0F0)? 0x04: 0) | \
76  (((n) & 0xCCCCCCCC)? 0x02: 0) | \
77  (((n) & 0xAAAAAAAA)? 0x01: 0) )
78 
79 // Index of the 'on' bit (assuming that there is only one).
80 // Even if multiple bits are 'on', result is in range of 0-63.
81 #define BIT_IDX_64(n) \
82  ((((n) & 0xFFFFFFFF00000000ULL)? 0x20: 0) | \
83  (((n) & 0xFFFF0000FFFF0000ULL)? 0x10: 0) | \
84  (((n) & 0xFF00FF00FF00FF00ULL)? 0x08: 0) | \
85  (((n) & 0xF0F0F0F0F0F0F0F0ULL)? 0x04: 0) | \
86  (((n) & 0xCCCCCCCCCCCCCCCCULL)? 0x02: 0) | \
87  (((n) & 0xAAAAAAAAAAAAAAAAULL)? 0x01: 0) )
88 
89 // Desctructive, assumes only one bit set in n32
90 // Deprecated in favor of BIT_IDX_32.
91 #define IDX_32(n32) \
92 { \
93  NvU32 idx = 0; \
94  if ((n32) & 0xFFFF0000) idx += 16; \
95  if ((n32) & 0xFF00FF00) idx += 8; \
96  if ((n32) & 0xF0F0F0F0) idx += 4; \
97  if ((n32) & 0xCCCCCCCC) idx += 2; \
98  if ((n32) & 0xAAAAAAAA) idx += 1; \
99  (n32) = idx; \
100 }
101 
102 // tegra mobile uses nvmisc_macros.h and can't access nvmisc.h... and sometimes both get included.
103 #ifndef _NVMISC_MACROS_H
104 // Use Coverity Annotation to mark issues as false positives/ignore when using single bit defines.
105 #define DRF_ISBIT(bitval,drf) \
106  ( /* coverity[identical_branches] */ \
107  bitval ? drf )
108 #define DEVICE_BASE(d) (0?d) // what's up with this name? totally non-parallel to the macros below
109 #define DEVICE_EXTENT(d) (1?d) // what's up with this name? totally non-parallel to the macros below
110 #define DRF_BASE(drf) (0?drf) // much better
111 #define DRF_EXTENT(drf) (1?drf) // much better
112 #define DRF_SHIFT(drf) ((DRF_ISBIT(0,drf)) % 32)
113 #define DRF_SHIFT_RT(drf) ((DRF_ISBIT(1,drf)) % 32)
114 #define DRF_MASK(drf) (0xFFFFFFFF>>(31-((DRF_ISBIT(1,drf)) % 32)+((DRF_ISBIT(0,drf)) % 32)))
115 #define DRF_SHIFTMASK(drf) (DRF_MASK(drf)<<(DRF_SHIFT(drf)))
116 #define DRF_SIZE(drf) (DRF_EXTENT(drf)-DRF_BASE(drf)+1)
117 
118 #define DRF_DEF(d,r,f,c) ((NV ## d ## r ## f ## c)<<DRF_SHIFT(NV ## d ## r ## f))
119 #define DRF_NUM(d,r,f,n) (((n)&DRF_MASK(NV ## d ## r ## f))<<DRF_SHIFT(NV ## d ## r ## f))
120 #define DRF_VAL(d,r,f,v) (((v)>>DRF_SHIFT(NV ## d ## r ## f))&DRF_MASK(NV ## d ## r ## f))
121 #endif
122 
123 // Signed version of DRF_VAL, which takes care of extending sign bit.
124 #define DRF_VAL_SIGNED(d,r,f,v) (((DRF_VAL(d,r,f,v) ^ (NVBIT(DRF_SIZE(NV ## d ## r ## f)-1)))) - (NVBIT(DRF_SIZE(NV ## d ## r ## f)-1)))
125 #define DRF_IDX_DEF(d,r,f,i,c) ((NV ## d ## r ## f ## c)<<DRF_SHIFT(NV##d##r##f(i)))
126 #define DRF_IDX_OFFSET_DEF(d,r,f,i,o,c) ((NV ## d ## r ## f ## c)<<DRF_SHIFT(NV##d##r##f(i,o)))
127 #define DRF_IDX_NUM(d,r,f,i,n) (((n)&DRF_MASK(NV##d##r##f(i)))<<DRF_SHIFT(NV##d##r##f(i)))
128 #define DRF_IDX_VAL(d,r,f,i,v) (((v)>>DRF_SHIFT(NV##d##r##f(i)))&DRF_MASK(NV##d##r##f(i)))
129 #define DRF_IDX_OFFSET_VAL(d,r,f,i,o,v) (((v)>>DRF_SHIFT(NV##d##r##f(i,o)))&DRF_MASK(NV##d##r##f(i,o)))
130 // Fractional version of DRF_VAL which reads Fx.y fixed point number (x.y)*z
131 #define DRF_VAL_FRAC(d,r,x,y,v,z) ((DRF_VAL(d,r,x,v)*z) + ((DRF_VAL(d,r,y,v)*z) / (1<<DRF_SIZE(NV##d##r##y))))
132 
133 //
134 // 64 Bit Versions
135 //
136 #define DRF_SHIFT64(drf) ((DRF_ISBIT(0,drf)) % 64)
137 #define DRF_MASK64(drf) (NV_U64_MAX>>(63-((DRF_ISBIT(1,drf)) % 64)+((DRF_ISBIT(0,drf)) % 64)))
138 #define DRF_SHIFTMASK64(drf) (DRF_MASK64(drf)<<(DRF_SHIFT64(drf)))
139 
140 #define DRF_DEF64(d,r,f,c) (((NvU64)(NV ## d ## r ## f ## c))<<DRF_SHIFT64(NV ## d ## r ## f))
141 #define DRF_NUM64(d,r,f,n) ((((NvU64)(n))&DRF_MASK64(NV ## d ## r ## f))<<DRF_SHIFT64(NV ## d ## r ## f))
142 #define DRF_VAL64(d,r,f,v) ((((NvU64)(v))>>DRF_SHIFT64(NV ## d ## r ## f))&DRF_MASK64(NV ## d ## r ## f))
143 
144 #define DRF_VAL_SIGNED64(d,r,f,v) (((DRF_VAL64(d,r,f,v) ^ (NVBIT64(DRF_SIZE(NV ## d ## r ## f)-1)))) - (NVBIT64(DRF_SIZE(NV ## d ## r ## f)-1)))
145 #define DRF_IDX_DEF64(d,r,f,i,c) (((NvU64)(NV ## d ## r ## f ## c))<<DRF_SHIFT64(NV##d##r##f(i)))
146 #define DRF_IDX_OFFSET_DEF64(d,r,f,i,o,c) ((NvU64)(NV ## d ## r ## f ## c)<<DRF_SHIFT64(NV##d##r##f(i,o)))
147 #define DRF_IDX_NUM64(d,r,f,i,n) ((((NvU64)(n))&DRF_MASK64(NV##d##r##f(i)))<<DRF_SHIFT64(NV##d##r##f(i)))
148 #define DRF_IDX_VAL64(d,r,f,i,v) ((((NvU64)(v))>>DRF_SHIFT64(NV##d##r##f(i)))&DRF_MASK64(NV##d##r##f(i)))
149 #define DRF_IDX_OFFSET_VAL64(d,r,f,i,o,v) (((NvU64)(v)>>DRF_SHIFT64(NV##d##r##f(i,o)))&DRF_MASK64(NV##d##r##f(i,o)))
150 
151 #define FLD_SET_DRF64(d,r,f,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_DEF64(d,r,f,c))
152 #define FLD_SET_DRF_NUM64(d,r,f,n,v) ((((NvU64)(v)) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_NUM64(d,r,f,n))
153 #define FLD_IDX_SET_DRF64(d,r,f,i,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_DEF64(d,r,f,i,c))
154 #define FLD_IDX_OFFSET_SET_DRF64(d,r,f,i,o,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i,o))) | DRF_IDX_OFFSET_DEF64(d,r,f,i,o,c))
155 #define FLD_IDX_SET_DRF_DEF64(d,r,f,i,c,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_DEF64(d,r,f,i,c))
156 #define FLD_IDX_SET_DRF_NUM64(d,r,f,i,n,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f(i))) | DRF_IDX_NUM64(d,r,f,i,n))
157 #define FLD_SET_DRF_IDX64(d,r,f,c,i,v) (((NvU64)(v) & ~DRF_SHIFTMASK64(NV##d##r##f)) | DRF_DEF64(d,r,f,c(i)))
158 
159 #define FLD_TEST_DRF64(d,r,f,c,v) (DRF_VAL64(d, r, f, v) == NV##d##r##f##c)
160 #define FLD_TEST_DRF_AND64(d,r,f,c,v) (DRF_VAL64(d, r, f, v) & NV##d##r##f##c)
161 #define FLD_TEST_DRF_NUM64(d,r,f,n,v) (DRF_VAL64(d, r, f, v) == n)
162 #define FLD_IDX_TEST_DRF64(d,r,f,i,c,v) (DRF_IDX_VAL64(d, r, f, i, v) == NV##d##r##f##c)
163 #define FLD_IDX_OFFSET_TEST_DRF64(d,r,f,i,o,c,v) (DRF_IDX_OFFSET_VAL64(d, r, f, i, o, v) == NV##d##r##f##c)
164 
165 //
166 // 32 Bit Versions
167 //
168 
169 #define FLD_SET_DRF(d,r,f,c,v) ((v & ~DRF_SHIFTMASK(NV##d##r##f)) | DRF_DEF(d,r,f,c))
170 #define FLD_SET_DRF_NUM(d,r,f,n,v) ((v & ~DRF_SHIFTMASK(NV##d##r##f)) | DRF_NUM(d,r,f,n))
171 // FLD_SET_DRF_DEF is deprecated! Use an explicit assignment with FLD_SET_DRF instead.
172 #define FLD_SET_DRF_DEF(d,r,f,c,v) (v = (v & ~DRF_SHIFTMASK(NV##d##r##f)) | DRF_DEF(d,r,f,c))
173 #define FLD_IDX_SET_DRF(d,r,f,i,c,v) ((v & ~DRF_SHIFTMASK(NV##d##r##f(i))) | DRF_IDX_DEF(d,r,f,i,c))
174 #define FLD_IDX_OFFSET_SET_DRF(d,r,f,i,o,c,v) ((v & ~DRF_SHIFTMASK(NV##d##r##f(i,o))) | DRF_IDX_OFFSET_DEF(d,r,f,i,o,c))
175 #define FLD_IDX_SET_DRF_DEF(d,r,f,i,c,v) ((v & ~DRF_SHIFTMASK(NV##d##r##f(i))) | DRF_IDX_DEF(d,r,f,i,c))
176 #define FLD_IDX_SET_DRF_NUM(d,r,f,i,n,v) ((v & ~DRF_SHIFTMASK(NV##d##r##f(i))) | DRF_IDX_NUM(d,r,f,i,n))
177 #define FLD_SET_DRF_IDX(d,r,f,c,i,v) ((v & ~DRF_SHIFTMASK(NV##d##r##f)) | DRF_DEF(d,r,f,c(i)))
178 
179 #define FLD_TEST_DRF(d,r,f,c,v) ((DRF_VAL(d, r, f, v) == NV##d##r##f##c))
180 #define FLD_TEST_DRF_AND(d,r,f,c,v) ((DRF_VAL(d, r, f, v) & NV##d##r##f##c))
181 #define FLD_TEST_DRF_NUM(d,r,f,n,v) ((DRF_VAL(d, r, f, v) == n))
182 #define FLD_IDX_TEST_DRF(d,r,f,i,c,v) ((DRF_IDX_VAL(d, r, f, i, v) == NV##d##r##f##c))
183 #define FLD_IDX_OFFSET_TEST_DRF(d,r,f,i,o,c,v) ((DRF_IDX_OFFSET_VAL(d, r, f, i, o, v) == NV##d##r##f##c))
184 
185 #define REF_DEF(drf,d) (((drf ## d)&DRF_MASK(drf))<<DRF_SHIFT(drf))
186 #define REF_VAL(drf,v) (((v)>>DRF_SHIFT(drf))&DRF_MASK(drf))
187 #define REF_NUM(drf,n) (((n)&DRF_MASK(drf))<<DRF_SHIFT(drf))
188 #define FLD_TEST_REF(drf,c,v) (REF_VAL(drf, v) == drf##c)
189 #define FLD_TEST_REF_AND(drf,c,v) (REF_VAL(drf, v) & drf##c)
190 #define FLD_SET_REF_NUM(drf,n,v) (((v) & ~DRF_SHIFTMASK(drf)) | REF_NUM(drf,n))
191 
192 #define CR_DRF_DEF(d,r,f,c) ((CR ## d ## r ## f ## c)<<DRF_SHIFT(CR ## d ## r ## f))
193 #define CR_DRF_NUM(d,r,f,n) (((n)&DRF_MASK(CR ## d ## r ## f))<<DRF_SHIFT(CR ## d ## r ## f))
194 #define CR_DRF_VAL(d,r,f,v) (((v)>>DRF_SHIFT(CR ## d ## r ## f))&DRF_MASK(CR ## d ## r ## f))
195 
196 // Multi-word (MW) field manipulations. For multi-word structures (e.g., Fermi SPH),
197 // fields may have bit numbers beyond 32. To avoid errors using "classic" multi-word macros,
198 // all the field extents are defined as "MW(X)". For example, MW(127:96) means
199 // the field is in bits 0-31 of word number 3 of the structure.
200 //
201 // DRF_VAL_MW() macro is meant to be used for native endian 32-bit aligned 32-bit word data,
202 // not for byte stream data.
203 //
204 // DRF_VAL_BS() macro is for byte stream data used in fbQueryBIOS_XXX().
205 //
206 #define DRF_EXPAND_MW(drf) drf // used to turn "MW(a:b)" into "a:b"
207 #define DRF_PICK_MW(drf,v) (v?DRF_EXPAND_##drf) // picks low or high bits
208 #define DRF_WORD_MW(drf) (DRF_PICK_MW(drf,0)/32) // which word in a multi-word array
209 #define DRF_BASE_MW(drf) (DRF_PICK_MW(drf,0)%32) // which start bit in the selected word?
210 #define DRF_EXTENT_MW(drf) (DRF_PICK_MW(drf,1)%32) // which end bit in the selected word
211 #define DRF_SHIFT_MW(drf) (DRF_PICK_MW(drf,0)%32)
212 #define DRF_MASK_MW(drf) (0xFFFFFFFF>>((31-(DRF_EXTENT_MW(drf))+(DRF_BASE_MW(drf)))%32))
213 #define DRF_SHIFTMASK_MW(drf) ((DRF_MASK_MW(drf))<<(DRF_SHIFT_MW(drf)))
214 #define DRF_SIZE_MW(drf) (DRF_EXTENT_MW(drf)-DRF_BASE_MW(drf)+1)
215 
216 #define DRF_DEF_MW(d,r,f,c) ((NV##d##r##f##c) << DRF_SHIFT_MW(NV##d##r##f))
217 #define DRF_NUM_MW(d,r,f,n) (((n)&DRF_MASK_MW(NV##d##r##f))<<DRF_SHIFT_MW(NV##d##r##f))
218 //
219 // DRF_VAL_MW is the ONLY multi-word macro which supports spanning. No other MW macro supports spanning currently
220 //
221 #define DRF_VAL_MW_1WORD(d,r,f,v) ((((v)[DRF_WORD_MW(NV##d##r##f)])>>DRF_SHIFT_MW(NV##d##r##f))&DRF_MASK_MW(NV##d##r##f))
222 #define DRF_SPANS(drf) ((DRF_PICK_MW(drf,0)/32) != (DRF_PICK_MW(drf,1)/32))
223 #define DRF_WORD_MW_LOW(drf) (DRF_PICK_MW(drf,0)/32)
224 #define DRF_WORD_MW_HIGH(drf) (DRF_PICK_MW(drf,1)/32)
225 #define DRF_MASK_MW_LOW(drf) (0xFFFFFFFF)
226 #define DRF_MASK_MW_HIGH(drf) (0xFFFFFFFF>>(31-(DRF_EXTENT_MW(drf))))
227 #define DRF_SHIFT_MW_LOW(drf) (DRF_PICK_MW(drf,0)%32)
228 #define DRF_SHIFT_MW_HIGH(drf) (0)
229 #define DRF_MERGE_SHIFT(drf) ((32-((DRF_PICK_MW(drf,0)%32)))%32)
230 #define DRF_VAL_MW_2WORD(d,r,f,v) (((((v)[DRF_WORD_MW_LOW(NV##d##r##f)])>>DRF_SHIFT_MW_LOW(NV##d##r##f))&DRF_MASK_MW_LOW(NV##d##r##f)) | \
231  (((((v)[DRF_WORD_MW_HIGH(NV##d##r##f)])>>DRF_SHIFT_MW_HIGH(NV##d##r##f))&DRF_MASK_MW_HIGH(NV##d##r##f)) << DRF_MERGE_SHIFT(NV##d##r##f)))
232 #define DRF_VAL_MW(d,r,f,v) ( DRF_SPANS(NV##d##r##f) ? DRF_VAL_MW_2WORD(d,r,f,v) : DRF_VAL_MW_1WORD(d,r,f,v) )
233 
234 #define DRF_IDX_DEF_MW(d,r,f,i,c) ((NV##d##r##f##c)<<DRF_SHIFT_MW(NV##d##r##f(i)))
235 #define DRF_IDX_NUM_MW(d,r,f,i,n) (((n)&DRF_MASK_MW(NV##d##r##f(i)))<<DRF_SHIFT_MW(NV##d##r##f(i)))
236 #define DRF_IDX_VAL_MW(d,r,f,i,v) ((((v)[DRF_WORD_MW(NV##d##r##f(i))])>>DRF_SHIFT_MW(NV##d##r##f(i)))&DRF_MASK_MW(NV##d##r##f(i)))
237 
238 //
239 // Logically OR all DRF_DEF constants indexed from zero to s (semiinclusive).
240 // Caution: Target variable v must be pre-initialized.
241 //
242 #define FLD_IDX_OR_DRF_DEF(d,r,f,c,s,v) \
243 do \
244 { NvU32 idx; \
245  for (idx = 0; idx < (NV ## d ## r ## f ## s); ++idx)\
246  { \
247  v |= DRF_IDX_DEF(d,r,f,idx,c); \
248  } \
249 } while(0)
250 
251 
252 #define FLD_MERGE_MW(drf,n,v) (((v)[DRF_WORD_MW(drf)] & ~DRF_SHIFTMASK_MW(drf)) | n)
253 #define FLD_ASSIGN_MW(drf,n,v) ((v)[DRF_WORD_MW(drf)] = FLD_MERGE_MW(drf, n, v))
254 #define FLD_IDX_MERGE_MW(drf,i,n,v) (((v)[DRF_WORD_MW(drf(i))] & ~DRF_SHIFTMASK_MW(drf(i))) | n)
255 #define FLD_IDX_ASSIGN_MW(drf,i,n,v) ((v)[DRF_WORD_MW(drf(i))] = FLD_MERGE_MW(drf(i), n, v))
256 
257 #define FLD_SET_DRF_MW(d,r,f,c,v) FLD_MERGE_MW(NV##d##r##f, DRF_DEF_MW(d,r,f,c), v)
258 #define FLD_SET_DRF_NUM_MW(d,r,f,n,v) FLD_ASSIGN_MW(NV##d##r##f, DRF_NUM_MW(d,r,f,n), v)
259 #define FLD_SET_DRF_DEF_MW(d,r,f,c,v) FLD_ASSIGN_MW(NV##d##r##f, DRF_DEF_MW(d,r,f,c), v)
260 #define FLD_IDX_SET_DRF_MW(d,r,f,i,c,v) FLD_IDX_MERGE_MW(NV##d##r##f, i, DRF_IDX_DEF_MW(d,r,f,i,c), v)
261 #define FLD_IDX_SET_DRF_DEF_MW(d,r,f,i,c,v) FLD_IDX_MERGE_MW(NV##d##r##f, i, DRF_IDX_DEF_MW(d,r,f,i,c), v)
262 #define FLD_IDX_SET_DRF_NUM_MW(d,r,f,i,n,v) FLD_IDX_ASSIGN_MW(NV##d##r##f, i, DRF_IDX_NUM_MW(d,r,f,i,n), v)
263 
264 #define FLD_TEST_DRF_MW(d,r,f,c,v) ((DRF_VAL_MW(d, r, f, v) == NV##d##r##f##c))
265 #define FLD_TEST_DRF_NUM_MW(d,r,f,n,v) ((DRF_VAL_MW(d, r, f, v) == n))
266 #define FLD_IDX_TEST_DRF_MW(d,r,f,i,c,v) ((DRF_IDX_VAL_MW(d, r, f, i, v) == NV##d##r##f##c))
267 
268 #define DRF_VAL_BS(d,r,f,v) ( DRF_SPANS(NV##d##r##f) ? DRF_VAL_BS_2WORD(d,r,f,v) : DRF_VAL_BS_1WORD(d,r,f,v) )
269 
270 //-------------------------------------------------------------------------//
271 // //
272 // Common defines for engine register reference wrappers //
273 // //
274 // New engine addressing can be created like: //
275 // #define ENG_REG_PMC(o,d,r) NV##d##r //
276 // #define ENG_IDX_REG_CE(o,d,i,r) CE_MAP(o,r,i) //
277 // //
278 // See FB_FBPA* for more examples //
279 //-------------------------------------------------------------------------//
280 
281 #define ENG_RD_REG(g,o,d,r) GPU_REG_RD32(g, ENG_REG##d(o,d,r))
282 #define ENG_WR_REG(g,o,d,r,v) GPU_REG_WR32(g, ENG_REG##d(o,d,r), v)
283 #define ENG_RD_DRF(g,o,d,r,f) ((GPU_REG_RD32(g, ENG_REG##d(o,d,r))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f))
284 #define ENG_WR_DRF_DEF(g,o,d,r,f,c) GPU_REG_WR32(g, ENG_REG##d(o,d,r),(GPU_REG_RD32(g,ENG_REG##d(o,d,r))&~(GPU_DRF_MASK(NV##d##r##f)<<GPU_DRF_SHIFT(NV##d##r##f)))|GPU_DRF_DEF(d,r,f,c))
285 #define ENG_WR_DRF_NUM(g,o,d,r,f,n) GPU_REG_WR32(g, ENG_REG##d(o,d,r),(GPU_REG_RD32(g,ENG_REG##d(o,d,r))&~(GPU_DRF_MASK(NV##d##r##f)<<GPU_DRF_SHIFT(NV##d##r##f)))|GPU_DRF_NUM(d,r,f,n))
286 #define ENG_TEST_DRF_DEF(g,o,d,r,f,c) (ENG_RD_DRF(g, o, d, r, f) == NV##d##r##f##c)
287 
288 #define ENG_RD_IDX_DRF(g,o,d,r,f,i) ((GPU_REG_RD32(g, ENG_REG##d(o,d,r(i)))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f))
289 #define ENG_TEST_IDX_DRF_DEF(g,o,d,r,f,c,i) (ENG_RD_IDX_DRF(g, o, d, r, f, i) == NV##d##r##f##c)
290 
291 #define ENG_IDX_RD_REG(g,o,d,i,r) GPU_REG_RD32(g, ENG_IDX_REG##d(o,d,i,r))
292 #define ENG_IDX_WR_REG(g,o,d,i,r,v) GPU_REG_WR32(g, ENG_IDX_REG##d(o,d,i,r), v)
293 
294 #define ENG_IDX_RD_DRF(g,o,d,i,r,f) ((GPU_REG_RD32(g, ENG_IDX_REG##d(o,d,i,r))>>GPU_DRF_SHIFT(NV ## d ## r ## f))&GPU_DRF_MASK(NV ## d ## r ## f))
295 
296 //
297 // DRF_READ_1WORD_BS() and DRF_READ_1WORD_BS_HIGH() do not read beyond the bytes that contain
298 // the requested value. Reading beyond the actual data causes a page fault panic when the
299 // immediately following page happened to be protected or not mapped.
300 //
301 #define DRF_VAL_BS_1WORD(d,r,f,v) ((DRF_READ_1WORD_BS(d,r,f,v)>>DRF_SHIFT_MW(NV##d##r##f))&DRF_MASK_MW(NV##d##r##f))
302 #define DRF_VAL_BS_2WORD(d,r,f,v) (((DRF_READ_4BYTE_BS(NV##d##r##f,v)>>DRF_SHIFT_MW_LOW(NV##d##r##f))&DRF_MASK_MW_LOW(NV##d##r##f)) | \
303  (((DRF_READ_1WORD_BS_HIGH(d,r,f,v)>>DRF_SHIFT_MW_HIGH(NV##d##r##f))&DRF_MASK_MW_HIGH(NV##d##r##f)) << DRF_MERGE_SHIFT(NV##d##r##f)))
304 
305 #define DRF_READ_1BYTE_BS(drf,v) ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4]))
306 #define DRF_READ_2BYTE_BS(drf,v) (DRF_READ_1BYTE_BS(drf,v)| \
307  ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+1])<<8))
308 #define DRF_READ_3BYTE_BS(drf,v) (DRF_READ_2BYTE_BS(drf,v)| \
309  ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+2])<<16))
310 #define DRF_READ_4BYTE_BS(drf,v) (DRF_READ_3BYTE_BS(drf,v)| \
311  ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW(drf)*4+3])<<24))
312 
313 #define DRF_READ_1BYTE_BS_HIGH(drf,v) ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4]))
314 #define DRF_READ_2BYTE_BS_HIGH(drf,v) (DRF_READ_1BYTE_BS_HIGH(drf,v)| \
315  ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+1])<<8))
316 #define DRF_READ_3BYTE_BS_HIGH(drf,v) (DRF_READ_2BYTE_BS_HIGH(drf,v)| \
317  ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+2])<<16))
318 #define DRF_READ_4BYTE_BS_HIGH(drf,v) (DRF_READ_3BYTE_BS_HIGH(drf,v)| \
319  ((NvU32)(((const NvU8*)(v))[DRF_WORD_MW_HIGH(drf)*4+3])<<24))
320 
321 // Calculate 2^n - 1 and avoid shift counter overflow
322 //
323 // On Windows amd64, 64 << 64 => 1
324 //
325 #define NV_TWO_N_MINUS_ONE(n) (((1ULL<<(n/2))<<((n+1)/2))-1)
326 
327 #define DRF_READ_1WORD_BS(d,r,f,v) \
328  ((DRF_EXTENT_MW(NV##d##r##f)<8)?DRF_READ_1BYTE_BS(NV##d##r##f,(v)): \
329  ((DRF_EXTENT_MW(NV##d##r##f)<16)?DRF_READ_2BYTE_BS(NV##d##r##f,(v)): \
330  ((DRF_EXTENT_MW(NV##d##r##f)<24)?DRF_READ_3BYTE_BS(NV##d##r##f,(v)): \
331  DRF_READ_4BYTE_BS(NV##d##r##f,(v)))))
332 
333 #define DRF_READ_1WORD_BS_HIGH(d,r,f,v) \
334  ((DRF_EXTENT_MW(NV##d##r##f)<8)?DRF_READ_1BYTE_BS_HIGH(NV##d##r##f,(v)): \
335  ((DRF_EXTENT_MW(NV##d##r##f)<16)?DRF_READ_2BYTE_BS_HIGH(NV##d##r##f,(v)): \
336  ((DRF_EXTENT_MW(NV##d##r##f)<24)?DRF_READ_3BYTE_BS_HIGH(NV##d##r##f,(v)): \
337  DRF_READ_4BYTE_BS_HIGH(NV##d##r##f,(v)))))
338 
339 #define BIN_2_GRAY(n) ((n)^((n)>>1))
340 // operates on a 64-bit data type
341 #define GRAY_2_BIN_64b(n) (n)^=(n)>>1; (n)^=(n)>>2; (n)^=(n)>>4; (n)^=(n)>>8; (n)^=(n)>>16; (n)^=(n)>>32;
342 
343 #define LOWESTBIT(x) ( (x) & (((x)-1) ^ (x)) )
344 // Destructive operation on n32
345 #define HIGHESTBIT(n32) \
346 { \
347  HIGHESTBITIDX_32(n32); \
348  n32 = NVBIT(n32); \
349 }
350 #define ONEBITSET(x) ( (x) && (((x) & ((x)-1)) == 0) )
351 
352 // Destructive operation on n32
353 #define NUMSETBITS_32(n32) \
354 { \
355  n32 = n32 - ((n32 >> 1) & 0x55555555); \
356  n32 = (n32 & 0x33333333) + ((n32 >> 2) & 0x33333333); \
357  n32 = (((n32 + (n32 >> 4)) & 0x0F0F0F0F) * 0x01010101) >> 24; \
358 }
359 
364 static NV_FORCEINLINE NvU32
365 nvPopCount32(const NvU32 x)
366 {
367  NvU32 temp = x;
368  temp = temp - ((temp >> 1) & 0x55555555);
369  temp = (temp & 0x33333333) + ((temp >> 2) & 0x33333333);
370  temp = (((temp + (temp >> 4)) & 0x0F0F0F0F) * 0x01010101) >> 24;
371  return temp;
372 }
373 
377 static NV_FORCEINLINE NvU32
378 nvPopCount64(const NvU64 x)
379 {
380  NvU64 temp = x;
381  temp = temp - ((temp >> 1) & 0x5555555555555555ull);
382  temp = (temp & 0x3333333333333333ull) + ((temp >> 2) & 0x3333333333333333ull);
383  temp = (temp + (temp >> 4)) & 0x0F0F0F0F0F0F0F0Full;
384  temp = (temp * 0x0101010101010101ull) >> 56;
385  return (NvU32)temp;
386 }
387 
399 static NV_FORCEINLINE NvU32
400 nvMaskPos32(const NvU32 mask, const NvU32 bitIdx)
401 {
402  return nvPopCount32(mask & (NVBIT32(bitIdx) - 1));
403 }
404 
405 // Destructive operation on n32
406 #define LOWESTBITIDX_32(n32) \
407 { \
408  n32 = LOWESTBIT(n32); \
409  IDX_32(n32); \
410 }
411 
412 // Destructive operation on n32
413 #define HIGHESTBITIDX_32(n32) \
414 { \
415  NvU32 count = 0; \
416  while (n32 >>= 1) \
417  { \
418  count++; \
419  } \
420  n32 = count; \
421 }
422 
423 // Destructive operation on n32
424 #define ROUNDUP_POW2(n32) \
425 { \
426  n32--; \
427  n32 |= n32 >> 1; \
428  n32 |= n32 >> 2; \
429  n32 |= n32 >> 4; \
430  n32 |= n32 >> 8; \
431  n32 |= n32 >> 16; \
432  n32++; \
433 }
434 
441 static NV_FORCEINLINE NvU32
442 nvNextPow2_U32(const NvU32 x)
443 {
444  NvU32 y = x;
445  y--;
446  y |= y >> 1;
447  y |= y >> 2;
448  y |= y >> 4;
449  y |= y >> 8;
450  y |= y >> 16;
451  y++;
452  return y;
453 }
454 
455 // Destructive operation on n64
456 #define ROUNDUP_POW2_U64(n64) \
457 { \
458  n64--; \
459  n64 |= n64 >> 1; \
460  n64 |= n64 >> 2; \
461  n64 |= n64 >> 4; \
462  n64 |= n64 >> 8; \
463  n64 |= n64 >> 16; \
464  n64 |= n64 >> 32; \
465  n64++; \
466 }
467 
468 #define NV_SWAP_U8(a,b) \
469 { \
470  NvU8 temp; \
471  temp = a; \
472  a = b; \
473  b = temp; \
474 }
475 
485 #define FOR_EACH_INDEX_IN_MASK(maskWidth,index,mask) \
486 { \
487  NvU##maskWidth lclMsk = (NvU##maskWidth)(mask); \
488  for (index = 0; lclMsk != 0; index++, lclMsk >>= 1) \
489  { \
490  if (((NvU##maskWidth)NVBIT64(0) & lclMsk) == 0) \
491  { \
492  continue; \
493  }
494 #define FOR_EACH_INDEX_IN_MASK_END \
495  } \
496 }
497 
498 //
499 // Size to use when declaring variable-sized arrays
500 //
501 #define NV_ANYSIZE_ARRAY 1
502 
503 //
504 // Returns ceil(a/b)
505 //
506 #define NV_CEIL(a,b) (((a)+(b)-1)/(b))
507 
508 // Clearer name for NV_CEIL
509 #ifndef NV_DIV_AND_CEIL
510 #define NV_DIV_AND_CEIL(a, b) NV_CEIL(a,b)
511 #endif
512 
513 #ifndef NV_MIN
514 #define NV_MIN(a, b) (((a) < (b)) ? (a) : (b))
515 #endif
516 
517 #ifndef NV_MAX
518 #define NV_MAX(a, b) (((a) > (b)) ? (a) : (b))
519 #endif
520 
521 //
522 // Returns absolute value of provided integer expression
523 //
524 #define NV_ABS(a) ((a)>=0?(a):(-(a)))
525 
526 //
527 // Returns 1 if input number is positive, 0 if 0 and -1 if negative. Avoid
528 // macro parameter as function call which will have side effects.
529 //
530 #define NV_SIGN(s) ((NvS8)(((s) > 0) - ((s) < 0)))
531 
532 //
533 // Returns 1 if input number is >= 0 or -1 otherwise. This assumes 0 has a
534 // positive sign.
535 //
536 #define NV_ZERO_SIGN(s) ((NvS8)((((s) >= 0) * 2) - 1))
537 
538 // Returns the offset (in bytes) of 'member' in struct 'type'.
539 #ifndef NV_OFFSETOF
540  #if defined(__GNUC__) && __GNUC__ > 3
541  #define NV_OFFSETOF(type, member) ((NvU32)__builtin_offsetof(type, member))
542  #else
543  #define NV_OFFSETOF(type, member) ((NvU32)(NvU64)&(((type *)0)->member)) // shouldn't we use PtrToUlong? But will need to include windows header.
544  #endif
545 #endif
546 
547 //
548 // Performs a rounded division of b into a (unsigned). For SIGNED version of
549 // NV_ROUNDED_DIV() macro check the comments in http://nvbugs/769777.
550 //
551 #define NV_UNSIGNED_ROUNDED_DIV(a,b) (((a) + ((b) / 2)) / (b))
552 
562 #define NV_UNSIGNED_DIV_CEIL(a, b) (((a) + (b - 1)) / (b))
563 
573 #define NV_RIGHT_SHIFT_ROUNDED(a, shift) \
574  (((a) >> (shift)) + !!((NVBIT((shift) - 1) & (a)) == NVBIT((shift) - 1)))
575 
576 //
577 // Power of 2 alignment.
578 // (Will give unexpected results if 'gran' is not a power of 2.)
579 //
580 #ifndef NV_ALIGN_DOWN
581 #define NV_ALIGN_DOWN(v, gran) ((v) & ~((gran) - 1))
582 #endif
583 
584 #ifndef NV_ALIGN_UP
585 #define NV_ALIGN_UP(v, gran) (((v) + ((gran) - 1)) & ~((gran)-1))
586 #endif
587 
588 #ifndef NV_IS_ALIGNED
589 #define NV_IS_ALIGNED(v, gran) (0 == ((v) & ((gran) - 1)))
590 #endif
591 
592 static NV_FORCEINLINE void *NVMISC_MEMSET(void *s, NvU8 c, NvLength n)
593 {
594  NvU8 *b = (NvU8 *) s;
595  NvLength i;
596 
597  for (i = 0; i < n; i++)
598  {
599  b[i] = c;
600  }
601 
602  return s;
603 }
604 
605 static NV_FORCEINLINE void *NVMISC_MEMCPY(void *dest, const void *src, NvLength n)
606 {
607  NvU8 *destByte = (NvU8 *) dest;
608  const NvU8 *srcByte = (const NvU8 *) src;
609  NvLength i;
610 
611  for (i = 0; i < n; i++)
612  {
613  destByte[i] = srcByte[i];
614  }
615 
616  return dest;
617 }
618 
619 static NV_FORCEINLINE char *NVMISC_STRNCPY(char *dest, const char *src, NvLength n)
620 {
621  NvLength i;
622 
623  for (i = 0; i < n; i++)
624  {
625  dest[i] = src[i];
626  if (src[i] == '\0')
627  {
628  break;
629  }
630  }
631 
632  for (; i < n; i++)
633  {
634  dest[i] = '\0';
635  }
636 
637  return dest;
638 }
639 
640 #ifdef __cplusplus
641 }
642 #endif //__cplusplus
643 
644 #endif // __NV_MISC_H
645 
nvPopCount64
static NV_FORCEINLINE NvU32 nvPopCount64(const NvU64 x)
Calculate number of bits set in a 64-bit unsigned integer.
Definition: nvmisc.h:378
NVMISC_STRNCPY
static NV_FORCEINLINE char * NVMISC_STRNCPY(char *dest, const char *src, NvLength n)
Definition: nvmisc.h:619
NVMISC_MEMCPY
static NV_FORCEINLINE void * NVMISC_MEMCPY(void *dest, const void *src, NvLength n)
Definition: nvmisc.h:605
nvPopCount32
static NV_FORCEINLINE NvU32 nvPopCount32(const NvU32 x)
Calculate number of bits set in a 32-bit unsigned integer.
Definition: nvmisc.h:365
nvtypes.h
nvMaskPos32
static NV_FORCEINLINE NvU32 nvMaskPos32(const NvU32 mask, const NvU32 bitIdx)
Determine how many bits are set below a bit index within a mask.
Definition: nvmisc.h:400
NVBIT32
#define NVBIT32(b)
Definition: nvmisc.h:67
nvNextPow2_U32
static NV_FORCEINLINE NvU32 nvNextPow2_U32(const NvU32 x)
Round up a 32-bit unsigned integer to the next power of 2.
Definition: nvmisc.h:442
NVMISC_MEMSET
static NV_FORCEINLINE void * NVMISC_MEMSET(void *s, NvU8 c, NvLength n)
Definition: nvmisc.h:592