NvSIPLInterrupts.hpp

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/*
 * SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
 *
 * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
 * property and proprietary rights in and to this material, related
 * documentation and any modifications thereto. Any use, reproduction,
 * disclosure or distribution of this material and related documentation
 * without an express license agreement from NVIDIA CORPORATION or
 * its affiliates is strictly prohibited.
 */
 
#ifndef NVSIPLINTERRUPTS_HPP
#define NVSIPLINTERRUPTS_HPP
 
namespace nvsipl
{
 
enum class InterruptCode : uint32_t {
    INTR_STATUS_DES_FAILURE = 0U,
    INTR_STATUS_DES_TIMEOUT = 1U,
    INTR_STATUS_DES_ERRB_ERR = 10U,
    INTR_STATUS_DES_LOCK_ERR = 11U,
 
    INTR_STATUS_PWR_FAILURE = 100U,
    INTR_STATUS_PWR_TIMEOUT = 101U,
 
    INTR_STATUS_SER_FAILURE = 1000U,
    INTR_STATUS_SER_TIMEOUT = 1001U,
 
    INTR_STATUS_SEN_FAILURE = 1100U,
    INTR_STATUS_SEN_TIMEOUT = 1101U,
 
    INTR_STATUS_PMIC_FAILURE = 1200U,
    INTR_STATUS_PMIC_TIMEOUT = 1201U,
 
    INTR_STATUS_EEPROM_FAILURE = 1300U,
    INTR_STATUS_EEPROM_TIMEOUT = 1301U,
 
    INTR_STATUS_LED_FAILURE = 1400U,
 
    INTR_STATUS_LED_TIMEOUT = 1401U,
 
    INTR_STATUS_FAILURE = 10000U,
    INTR_STATUS_TIMEOUT = 10001U,
    INTR_STATUS_LOCALIZATION_FAILURE = 10002U,
};
 
}  // namespace nvsipl
 
 
#endif // NVSIPLINTERRUPTS_HPP