NvSIPLCapStructs.h

Go to the documentation of this file.

/*
 * SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
 *
 * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
 * property and proprietary rights in and to this material, related
 * documentation and any modifications thereto. Any use, reproduction,
 * disclosure or distribution of this material and related documentation
 * without an express license agreement from NVIDIA CORPORATION or
 * its affiliates is strictly prohibited.
 */
 
#ifndef NVSIPL_CAP_STRUCTS_H
#define NVSIPL_CAP_STRUCTS_H
 
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
 
enum NvSiplCapInterfaceType {
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_A,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_B,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_AB,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_C,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_D,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_CD,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_E,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_F,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_EF,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_G,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_H,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_GH,
#if (NV_IS_SAFETY == 0)
 
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_A1,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_B1,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_C1,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_D1,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_E1,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_F1,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_G1,
    NVSIPL_CAP_CSI_INTERFACE_TYPE_CSI_H1,
#endif
    NVSIPL_CAP_CSI_INTERFACE_TYPE_MAX,
};
 
enum NvSiplCapInputFormatType {
    NVSIPL_CAP_INPUT_FORMAT_TYPE_YUV422,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_YUV422_10,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_YUV444,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_RGB888,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW6,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW7,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW8,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW10,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW12,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW14,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW16,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW20,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_USER_DEFINED_1,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_USER_DEFINED_2,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_USER_DEFINED_3,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_USER_DEFINED_4,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_USER_DEFINED_5,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_USER_DEFINED_6,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_USER_DEFINED_7,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_USER_DEFINED_8,
    NVSIPL_CAP_INPUT_FORMAT_TYPE_RAW12RJ,
};
 
enum NvSiplBitsPerPixel {
    NVSIPL_BITS_PER_PIXEL_8 = 0,
    NVSIPL_BITS_PER_PIXEL_10,
    NVSIPL_BITS_PER_PIXEL_12,
    NVSIPL_BITS_PER_PIXEL_14,
    NVSIPL_BITS_PER_PIXEL_16,
    NVSIPL_BITS_PER_PIXEL_20
};
 
enum NvSiplCapCsiPhyMode {
    NVSIPL_CAP_CSI_DPHY_MODE = 0,
    NVSIPL_CAP_CSI_CPHY_MODE
};
 
#define NVSIPL_CAP_MIN_IMAGE_WIDTH       640U
 
#define NVSIPL_CAP_MAX_IMAGE_WIDTH       32766U
 
#define NVSIPL_CAP_MIN_IMAGE_HEIGHT      480U
 
#define NVSIPL_CAP_MAX_IMAGE_HEIGHT      32766U
 
#define NVSIPL_CAP_MIN_FRAME_RATE        10U
 
#define NVSIPL_CAP_MAX_FRAME_RATE        60U
 
#define NVSIPL_PIXEL_ORDER_LUMA                (0x00000001U)
 
#define NVSIPL_PIXEL_ORDER_YUV                 (0x00000002U)
 
#define NVSIPL_PIXEL_ORDER_YVU                 (0x00000003U)
 
#define NVSIPL_PIXEL_ORDER_YUYV                (0x00000004U)
 
#define NVSIPL_PIXEL_ORDER_YVYU                (0x00000005U)
 
#define NVSIPL_PIXEL_ORDER_VYUY                (0x00000006U)
 
#define NVSIPL_PIXEL_ORDER_UYVY                (0x00000007U)
 
#define NVSIPL_PIXEL_ORDER_XUYV                (0x00000008U)
 
#define NVSIPL_PIXEL_ORDER_XYUV                (0x00000009U)
 
#define NVSIPL_PIXEL_ORDER_VUYX                (0x0000000AU)
 
#define NVSIPL_PIXEL_ORDER_ALPHA               (0x00000011U)
 
#define NVSIPL_PIXEL_ORDER_RGBA                (0x00000012U)
 
#define NVSIPL_PIXEL_ORDER_ARGB                (0x00000013U)
 
#define NVSIPL_PIXEL_ORDER_BGRA                (0x00000014U)
 
#define NVSIPL_PIXEL_ORDER_RG                  (0x00000015U)
 
#define NVSIPL_PIXEL_ORDER_RGGB                (0x00000021U)
 
#define NVSIPL_PIXEL_ORDER_BGGR                (0x00000022U)
 
#define NVSIPL_PIXEL_ORDER_GRBG                (0x00000023U)
 
#define NVSIPL_PIXEL_ORDER_GBRG                (0x00000024U)
 
#define NVSIPL_PIXEL_ORDER_RCCB                (0x00000025U)
 
#define NVSIPL_PIXEL_ORDER_BCCR                (0x00000026U)
 
#define NVSIPL_PIXEL_ORDER_CRBC                (0x00000027U)
 
#define NVSIPL_PIXEL_ORDER_CBRC                (0x00000028U)
 
#define NVSIPL_PIXEL_ORDER_RCCC                (0x00000029U)
 
#define NVSIPL_PIXEL_ORDER_CCCR                (0x0000002AU)
 
#define NVSIPL_PIXEL_ORDER_CRCC                (0x0000002BU)
 
#define NVSIPL_PIXEL_ORDER_CCRC                (0x0000002CU)
 
#define NVSIPL_PIXEL_ORDER_CCCC                (0x0000002DU)
 
#define NVSIPL_PIXEL_ORDER_BGGI_RGGI                (0x0000002EU)
 
#define NVSIPL_PIXEL_ORDER_GBIG_GRIG                (0x0000002FU)
 
#define NVSIPL_PIXEL_ORDER_GIBG_GIRG                (0x00000030U)
 
#define NVSIPL_PIXEL_ORDER_IGGB_IGGR                (0x00000031U)
 
#define NVSIPL_PIXEL_ORDER_RGGI_BGGI                (0x00000032U)
 
#define NVSIPL_PIXEL_ORDER_GRIG_GBIG                (0x00000033U)
 
#define NVSIPL_PIXEL_ORDER_GIRG_GIBG                (0x00000034U)
 
#define NVSIPL_PIXEL_ORDER_IGGR_IGGB                (0x00000035U)
 
struct NvSiplCapInputFormat {
    enum NvSiplCapInputFormatType inputFormatType;
    enum NvSiplBitsPerPixel bitsPerPixel;
};
 
#ifdef __cplusplus
}     /* extern "C" */
#endif /* __cplusplus */
 
#endif /* NVSIPL_CAP_STRUCTS_H */