DLA Device Tree

The nvdla0 and nvdla1 nodes contain the configuration parameters needed for initializing the DLA driver.

Sample Device Tree

This section provides the sample entries for the nvdla0 and nvdla1 nodes.

nvdla0: nvdla0@15880000 {
    compatible = "nvidia,tegra234-nvdla";
    power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DLAA>;
    reg = <0x0 0x15880000 0x0 0x00040000>;
    interrupts = <0 236 0x04>;

    resets = <&bpmp_resets TEGRA234_RESET_DLA0>;
    clocks = <&bpmp_clks TEGRA234_CLK_DLA0_CORE>,
         <&bpmp_clks TEGRA234_CLK_DLA0_FALCON>;
    clock-names = "nvdla0", "nvdla0_flcn";

    iommus = <&smmu_niso1 TEGRA_SID_NISO1_NVDLA0>;
    status = "okay";

nvdla1: nvdla1@158c0000 {
    compatible = "nvidia,tegra234-nvdla";
    power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DLAB>;
    reg = <0x0 0x158c0000 0x0 0x00040000>;
    interrupts = <0 237 0x04>;

    resets = <&bpmp_resets TEGRA234_RESET_DLA1>;
    clocks = <&bpmp_clks TEGRA234_CLK_DLA1_CORE>,
         <&bpmp_clks TEGRA234_CLK_DLA1_FALCON>;
    clock-names = "nvdla1", "nvdla1_flcn";

    iommus = <&smmu_niso0 TEGRA_SID_NISO0_NVDLA1>;
    status = "okay";

DLA Device Tree Properties

Property Description Customizable Optional Value
compatible A unique string to identify the DLA DT node No No nvidia,tegra234-nvdla
power-domains A phandle and PM domain specifier as defined by bindings of the power controller specified by phandle No No TEGRA234_POWER_DOMAIN_DLA[A|B]
reg Physical base address and length of the controller’s registers No No Must contain two entries: one for the physical address and other for the length.
interrupts Describes the IRQ number and IRQ type No No Must contain an entry for each interrupt.
resets List of phandle and reset specifier pairs, one pair for each reset signal that affects the device, or that the device manages No No TEGRA234_RESET_DLA[0|1]
clocks the type of clocks ids that are supported No No TEGRA234_CLK_DLA[0|1]_CORE and TEGRA234_CLK_DLA[0|1]_FALCON
clock-names List of clock input name strings sorted in the same order as the clocks property. Consumer?s drivers will use clock-names to match clock input names with clocks specifiers No Yes nvdla[0|1] and nvdla[0|1]_flcn
iommus A list of phandle and IOMMU specifier pairs that describe the IOMMU master interfaces of the device. One entry in the list describes one master interface of the device No No TEGRA_SID_NISO1_NVDLA0, TEGRA_SID_NISO0_NVDLA1
dma-coherent Present if DMA operations are coherent No No N/A
status status of NVDLA nodes No Yes okay or disabled