Display Device Tree

The NvDisplay driver uses the following device tree nodes and properties. Properties customizable are marked accordingly for each property used. Nodes used in NvDisplay drivers for QNX are as follows.

NvDisplay

nvdisplay node, contains configuration parameters for initializing the NvDisplay driver.

nvdisplay: display@13800000 {
compatible = "nvidia,tegra234-display";
power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>; nvidia,num-dpaux-instance = <1>;
reg-names = "nvdisplay", "dpaux0", "hdacodec", "mipical"; reg = <0x0 0x13800000 0x0 0xEFFFF /* nvdisplay */
0x0 0x155C0000 0x0 0xFFFF /* dpaux0 */ 0x0 0x0242c000 0x0 0x1000 /* hdacodec */ 0x0 0x03990000 0x0 0x10000>; /* mipical */
interrupt-names = "nvdisplay", "dpaux0", "hdacodec"; interrupts = <0 416 4
0 419 4
0 61 4>;
nvidia,bpmp = <&bpmp>;
clocks = <&bpmp_clks TEGRA234_CLK_HUB>,
<&bpmp_clks TEGRA234_CLK_DISP>,
<&bpmp_clks TEGRA234_CLK_NVDISPLAY_P0>,
<&bpmp_clks TEGRA234_CLK_NVDISPLAY_P1>,
<&bpmp_clks TEGRA234_CLK_DPAUX>,
<&bpmp_clks TEGRA234_CLK_FUSE>,
<&bpmp_clks TEGRA234_CLK_DSIPLL_VCO>,
<&bpmp_clks TEGRA234_CLK_DSIPLL_CLKOUTPN>,
<&bpmp_clks TEGRA234_CLK_DSIPLL_CLKOUTA>,
<&bpmp_clks TEGRA234_CLK_SPPLL0_VCO>,
<&bpmp_clks TEGRA234_CLK_SPPLL0_CLKOUTPN>,
<&bpmp_clks TEGRA234_CLK_SPPLL0_CLKOUTA>,
<&bpmp_clks TEGRA234_CLK_SPPLL0_CLKOUTB>,
<&bpmp_clks TEGRA234_CLK_SPPLL0_DIV10>,
<&bpmp_clks TEGRA234_CLK_SPPLL0_DIV25>,
<&bpmp_clks TEGRA234_CLK_SPPLL0_DIV27PN>,
<&bpmp_clks TEGRA234_CLK_SPPLL1_VCO>,
<&bpmp_clks TEGRA234_CLK_SPPLL1_CLKOUTPN>,
<&bpmp_clks TEGRA234_CLK_SPPLL1_DIV27PN>,
<&bpmp_clks TEGRA234_CLK_VPLL0_REF>,
<&bpmp_clks TEGRA234_CLK_VPLL0>,
<&bpmp_clks TEGRA234_CLK_VPLL1>,
<&bpmp_clks TEGRA234_CLK_NVDISPLAY_P0_REF>,
<&bpmp_clks TEGRA234_CLK_RG0>,
<&bpmp_clks TEGRA234_CLK_RG1>,
<&bpmp_clks TEGRA234_CLK_DISPPLL>,
<&bpmp_clks TEGRA234_CLK_DISPHUBPLL>,
<&bpmp_clks TEGRA234_CLK_DSI_LP>,
<&bpmp_clks TEGRA234_CLK_DSI_CORE>,
<&bpmp_clks TEGRA234_CLK_DSI_PIXEL>,
<&bpmp_clks TEGRA234_CLK_PRE_SOR0>,
<&bpmp_clks TEGRA234_CLK_PRE_SOR1>,
<&bpmp_clks TEGRA234_CLK_DP_LINK_REF>,
<&bpmp_clks TEGRA234_CLK_SOR_LINKA_INPUT>,
<&bpmp_clks TEGRA234_CLK_SOR_LINKA_AFIFO>,
<&bpmp_clks TEGRA234_CLK_SOR_LINKA_AFIFO_M>,
<&bpmp_clks TEGRA234_CLK_RG0_M>,
<&bpmp_clks TEGRA234_CLK_RG1_M>,
<&bpmp_clks TEGRA234_CLK_SOR0_M>,
<&bpmp_clks TEGRA234_CLK_SOR1_M>,
<&bpmp_clks TEGRA234_CLK_PLLHUB>,
<&bpmp_clks TEGRA234_CLK_SOR0>,
<&bpmp_clks TEGRA234_CLK_SOR1>,
<&bpmp_clks TEGRA234_CLK_SOR_PAD_INPUT>,
<&bpmp_clks TEGRA234_CLK_PRE_SF0>,
<&bpmp_clks TEGRA234_CLK_SF0>,
<&bpmp_clks TEGRA234_CLK_SF1>,
<&bpmp_clks TEGRA234_CLK_DSI_PAD_INPUT>,
<&bpmp_clks TEGRA234_CLK_PRE_SOR0_REF>,
<&bpmp_clks TEGRA234_CLK_PRE_SOR1_REF>,
<&bpmp_clks TEGRA234_CLK_SOR0_PLL_REF>,
<&bpmp_clks TEGRA234_CLK_SOR1_PLL_REF>,
<&bpmp_clks TEGRA234_CLK_SOR0_REF>,
<&bpmp_clks TEGRA234_CLK_SOR1_REF>,
<&bpmp_clks TEGRA234_CLK_OSC>,
<&bpmp_clks TEGRA234_CLK_DSC>,
<&bpmp_clks TEGRA234_CLK_MAUD>,
<&bpmp_clks TEGRA234_CLK_AZA_2XBIT>,
<&bpmp_clks TEGRA234_CLK_AZA_BIT>,
<&bpmp_clks TEGRA234_CLK_MIPI_CAL>,
<&bpmp_clks TEGRA234_CLK_UART_FST_MIPI_CAL>,
<&bpmp_clks TEGRA234_CLK_SOR0_DIV>; clock-names = "nvdisplayhub_clk",
"nvdisplay_disp_clk", "nvdisplay_p0_clk", "nvdisplay_p1_clk", "dpaux0_clk", "fuse_clk", "dsipll_vco_clk", "dsipll_clkoutpn_clk", "dsipll_clkouta_clk", "sppll0_vco_clk", "sppll0_clkoutpn_clk", "sppll0_clkouta_clk", "sppll0_clkoutb_clk", "sppll0_div10_clk", "sppll0_div25_clk", "sppll0_div27_clk",
"sppll1_vco_clk", "sppll1_clkoutpn_clk", "sppll1_div27_clk", "vpll0_ref_clk", "vpll0_clk", "vpll1_clk",
"nvdisplay_p0_ref_clk", "rg0_clk",
"rg1_clk", "disppll_clk", "disphubpll_clk", "dsi_lp_clk", "dsi_core_clk", "dsi_pixel_clk", "pre_sor0_clk", "pre_sor1_clk", "dp_link_ref_clk", "sor_linka_input_clk", "sor_linka_afifo_clk",
"sor_linka_afifo_m_clk", "rg0_m_clk", "rg1_m_clk", "sor0_m_clk", "sor1_m_clk", "pllhub_clk",
"sor0_clk", "sor1_clk", "sor_pad_input_clk", "pre_sf0_clk", "sf0_clk",
"sf1_clk", "dsi_pad_input_clk", "pre_sor0_ref_clk", "pre_sor1_ref_clk", "sor0_ref_pll_clk", "sor1_ref_pll_clk", "sor0_ref_clk", "sor1_ref_clk", "osc_clk",
"dsc_clk", "maud_clk", "aza_2xbit_clk", "aza_bit_clk", "mipi_cal_clk",
"uart_fst_mipi_cal_clk", "sor0_div_clk";
resets = <&bpmp_resets TEGRA234_RESET_NVDISPLAY>,
<&bpmp_resets TEGRA234_RESET_DPAUX>,
<&bpmp_resets TEGRA234_RESET_DSI_CORE>,
<&bpmp_resets TEGRA234_RESET_MIPI_CAL>;
reset-names = "nvdisplay_reset",
"dpaux0_reset", "dsi_core_reset", "mipi_cal_reset";
status = "disabled";
nvidia,disp-sw-soc-chip-id = <0x2350>;
#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR>,
<&mc TEGRA234_MEMORY_CLIENT_NVDISPLAYR1>;
interconnect-names = "dma-mem", "read-1";
#endif
iommus = <&smmu_iso TEGRA_SID_ISO_NVDISPLAY>; non-coherent;
nvdisplay-niso {
compatible = "nvidia,tegra234-display-niso";
iommus = <&smmu_niso0 TEGRA_SID_NISO0_NVDISPLAY>; dma-coherent;
};
dsi {
compatible = "nvidia,tegra234-dsi"; nvidia,active-panel = "NULL"; status = "disabled";
};
};

compatible:

Description: - `compatible` contains the unique string to identify the external NvDisplay DT node.

Customizable: No

Optional: No

Value: " nvidia,tegra234-display"

power-domains:

Description: - `power-domains` identifies the power domain display belongs to.

Customizable: No

Optional: No

Value: <&bpmp TEGRA234_POWER_DOMAIN_DISP>

nvidia,num-dpaux-instance:

Description: - num-dpaux-instance specifies the number of DPAUX pads on the underlying platform.

Customizable: No

Optional: No

Value: <1>

reg-names:

Description: - reg-names mentions all of the MMIO device apertures that the display driver needs access to.

Customizable: No

Optional: No

Value: Must contain an entry for all the register names

  • nvdisplay
  • dpaux0
  • hdacodec (Not used by QNX driver)
  • mipical (Not used by QNX driver)

reg:

Description: - Physical base address and length of the controller's registers

Customizable: No

Optional: No

Value: Tuple in the form of address and length/size that describes the address range. Must contain an entry for each register entry mentioned in the “reg” field:

  • 0x0 0x13800000 0x0 0xEFFFF
  • 0x0 0x155C0000 0x0 0xFFFF
  • 0x0 0x0242c000 0x0 0x1000 (corresponds to hdacodec, Not used by QNX driver)
  • 0x0 0x03990000 0x0 0x10000 (corresponds to mipical, Not used by QNX driver)

interrupt-names:

Description: - Mentions the type of interrupts supported by NvDisplay node

Customizable: No

Optional: No

Value: Must contain the following entries:

  • nvdisplay
  • dpaux0
  • hdacodec (Not used by QNX driver)

interrupts:

Description: `interrupts` holds the IRQ number and IRQ type connected to NvDisplay.

Customizable: No

Optional: No

Value: Must contain an entry for each entry in interrupt-names.

0 416 4

0 419 4

0 61 4

nvidia,bpmp:

Description: BPMP device, needed for NvDisplay

Customizable: No

Optional: No

Value: bpmp

clocks:

Description: `clocks` holds the type of clock IDs supported by NvDisplay.

Customizable: No

Optional: No

Value: <&bpmp_clks TEGRA234_CLK_HUB>,

<&bpmp_clks TEGRA234_CLK_DISP>,

<&bpmp_clks TEGRA234_CLK_NVDISPLAY_P0>,

<&bpmp_clks TEGRA234_CLK_NVDISPLAY_P1>,

<&bpmp_clks TEGRA234_CLK_DPAUX>,

<&bpmp_clks TEGRA234_CLK_FUSE>,

<&bpmp_clks TEGRA234_CLK_DSIPLL_VCO>,

<&bpmp_clks TEGRA234_CLK_DSIPLL_CLKOUTPN>,

<&bpmp_clks TEGRA234_CLK_DSIPLL_CLKOUTA>,

<&bpmp_clks TEGRA234_CLK_SPPLL0_VCO>,

<&bpmp_clks TEGRA234_CLK_SPPLL0_CLKOUTPN>,

<&bpmp_clks TEGRA234_CLK_SPPLL0_CLKOUTA>,

<&bpmp_clks TEGRA234_CLK_SPPLL0_CLKOUTB>,

<&bpmp_clks TEGRA234_CLK_SPPLL0_DIV10>,

<&bpmp_clks TEGRA234_CLK_SPPLL0_DIV25>,

<&bpmp_clks TEGRA234_CLK_SPPLL0_DIV27PN>,

<&bpmp_clks TEGRA234_CLK_SPPLL1_VCO>,

<&bpmp_clks TEGRA234_CLK_SPPLL1_CLKOUTPN>,

<&bpmp_clks TEGRA234_CLK_SPPLL1_DIV27PN>,

<&bpmp_clks TEGRA234_CLK_VPLL0_REF>,

<&bpmp_clks TEGRA234_CLK_VPLL0>,

<&bpmp_clks TEGRA234_CLK_VPLL1>,

<&bpmp_clks TEGRA234_CLK_NVDISPLAY_P0_REF>,

<&bpmp_clks TEGRA234_CLK_RG0>,

<&bpmp_clks TEGRA234_CLK_RG1>,

<&bpmp_clks TEGRA234_CLK_DISPPLL>,

<&bpmp_clks TEGRA234_CLK_DISPHUBPLL>,

<&bpmp_clks TEGRA234_CLK_DSI_LP>,

<&bpmp_clks TEGRA234_CLK_DSI_CORE>,

<&bpmp_clks TEGRA234_CLK_DSI_PIXEL>,

<&bpmp_clks TEGRA234_CLK_PRE_SOR0>,

<&bpmp_clks TEGRA234_CLK_PRE_SOR1>,

<&bpmp_clks TEGRA234_CLK_DP_LINK_REF>,

<&bpmp_clks TEGRA234_CLK_SOR_LINKA_INPUT>,

<&bpmp_clks TEGRA234_CLK_SOR_LINKA_AFIFO>,

<&bpmp_clks TEGRA234_CLK_SOR_LINKA_AFIFO_M>,

<&bpmp_clks TEGRA234_CLK_RG0_M>,

<&bpmp_clks TEGRA234_CLK_RG1_M>,

<&bpmp_clks TEGRA234_CLK_SOR0_M>,

<&bpmp_clks TEGRA234_CLK_SOR1_M>,

<&bpmp_clks TEGRA234_CLK_PLLHUB>,

<&bpmp_clks TEGRA234_CLK_SOR0>,

<&bpmp_clks TEGRA234_CLK_SOR1>,

<&bpmp_clks TEGRA234_CLK_SOR_PAD_INPUT>,

<&bpmp_clks TEGRA234_CLK_PRE_SF0>,

<&bpmp_clks TEGRA234_CLK_SF0>,

<&bpmp_clks TEGRA234_CLK_SF1>,

<&bpmp_clks TEGRA234_CLK_DSI_PAD_INPUT>,

<&bpmp_clks TEGRA234_CLK_PRE_SOR0_REF>,

<&bpmp_clks TEGRA234_CLK_PRE_SOR1_REF>,

<&bpmp_clks TEGRA234_CLK_SOR0_PLL_REF>,

<&bpmp_clks TEGRA234_CLK_SOR1_PLL_REF>,

<&bpmp_clks TEGRA234_CLK_SOR0_REF>,

<&bpmp_clks TEGRA234_CLK_SOR1_REF>,

<&bpmp_clks TEGRA234_CLK_OSC>,

<&bpmp_clks TEGRA234_CLK_DSC>,

<&bpmp_clks TEGRA234_CLK_MAUD>,

<&bpmp_clks TEGRA234_CLK_AZA_2XBIT>,

<&bpmp_clks TEGRA234_CLK_AZA_BIT>,

<&bpmp_clks TEGRA234_CLK_MIPI_CAL>,

<&bpmp_clks TEGRA234_CLK_UART_FST_MIPI_CAL>,

<&bpmp_clks TEGRA234_CLK_SOR0_DIV>;

clock-names:

Description: List of clock input name strings sorted in the same order as the clocks property. Consumer’s drivers will use clock-names to match clock input names with clocks specifiers

Customizable: No

Optional: No

Value: "nvdisplayhub_clk", "nvdisplay_disp_clk", "nvdisplay_p0_clk", "nvdisplay_p1_clk", "dpaux0_clk", "fuse_clk", "dsipll_vco_clk", "dsipll_clkoutpn_clk", "dsipll_clkouta_clk", "sppll0_vco_clk", "sppll0_clkoutpn_clk", "sppll0_clkouta_clk", "sppll0_clkoutb_clk", "sppll0_div10_clk", "sppll0_div25_clk", "sppll0_div27_clk", "sppll1_vco_clk", "sppll1_clkoutpn_clk", "sppll1_div27_clk", "vpll0_ref_clk", "vpll0_clk", "vpll1_clk", "nvdisplay_p0_ref_clk", "rg0_clk", "rg1_clk", "disppll_clk", "disphubpll_clk", "dsi_lp_clk", "dsi_core_clk", "dsi_pixel_clk", "pre_sor0_clk", "pre_sor1_clk", "dp_link_ref_clk", "sor_linka_input_clk", "sor_linka_afifo_clk", "sor_linka_afifo_m_clk", "rg0_m_clk", "rg1_m_clk", "sor0_m_clk", "sor1_m_clk", "pllhub_clk", "sor0_clk", "sor1_clk", "sor_pad_input_clk", "pre_sf0_clk", "sf0_clk", "sf1_clk", "dsi_pad_input_clk", "pre_sor0_ref_clk", "pre_sor1_ref_clk", "sor0_ref_pll_clk", "sor1_ref_pll_clk", "sor0_ref_clk", "sor1_ref_clk", "osc_clk", "dsc_clk", "maud_clk", "aza_2xbit_clk", "aza_bit_clk", "mipi_cal_clk", "uart_fst_mipi_cal_clk", "sor0_div_clk";

resets:

Description: List of phandle and reset specifier pairs, one pair for each reset signal that affects the device, or that the device manages.

Customizable: No

Optional: No

Value:

  • TEGRA234_RESET_NVDISPLAY
  • TEGRA234_RESET_DPAUX
  • TEGRA234_RESET_DSI_CORE (Not used by QNX driver)
  • TEGRA234_RESET_MIPI_CAL (Not used by QNX driver)

reset-names:

Description: The name of the resets mentioned in the “resets” field

Customizable: No

Optional: No

Value: Must contain an entry for each value in the “resets” field:

  • nvdisplay_reset
  • dpaux0_reset
  • dsi_core_reset (Not used by QNX driver)
  • mipi_cal_reset (Not used by QNX driver)

status:

Description: Holds the status of NvDisplay

Customizable: No

Optional: No

Value: “okay” or “disabled”

nvidia,disp-sw-soc-chip-id:

Description: Mentions the SOC SW Chip ID

Customizable: No

Optional: No

Value: 0x2350

interconnects:

Description: Specifies the bandwidth of the clients used by NvDisplay. This is only if TEGRA_IOMMU_DT_VERSION is greater or equal to DT_VERSION_2. Not used on AV+L or AV+Q.

Customizable: No

Optional: No

Value:

  • TEGRA234_MEMORY_CLIENT_NVDISPLAYR
  • TEGRA234_MEMORY_CLIENT_NVDISPLAYR1

interconnect-names:

Description: Mentions the names of the interconnects used by NvDisplay. This is only if TEGRA_IOMMU_DT_VERSION is greater or equal to DT_VERSION_2.

Customizable: No

Optional: No

Value: Must contain an entry for each value in “interconnects” field

  • dma-mem
  • read-1

iommus:

Description: Mentions the name of the IOMMU used by NvDisplay for ISO traffic.

Customizable: No

Optional: No

Value: TEGRA_SID_ISO_NVDISPLAY

non-coherent:

Description: Present because NvDisplay ISO accesses to DRAM are non-coherent.

Customizable: No

Optional: No

Value: N/A

nvdisplay-niso node

Contains details about the IOMMU instance used by NvDisplay for NISO memory accesses.

nvdisplay-niso {
compatible = "nvidia,tegra234-display-niso";
iommus = <&smmu_niso0 TEGRA_SID_NISO0_NVDISPLAY>; dma-coherent;
};

compatible:

Description: - `compatible` contains the unique string to identify the external NvDisplay-NISO DT node

Customizable: No

Optional: No

Value: " nvidia,tegra234-display-niso"

iommus:

Description: Mentions the name of the IOMMU used by the NvDisplay-NISO node.

Customizable: No

Optional: No

Value:
  • TEGRA_SID_NISO0_NVDISPLAY

dma-coherent:

Description: Present because NvDisplay NISO memory accesses are DMA-coherent.

Customizable: No

Optional: No

Value: N/A

dsi node

Contains details about DSI, used by NvDisplay node. Is not used in automotive QNX.

dsi {
compatible = "nvidia,tegra234-dsi"; nvidia,active-panel = "NULL"; status = "disabled";
};

compatible:

Description: - `compatible` contains the unique string to identify the external NvDisplay-DSI DT node.

Customizable: No

Optional: No

Value: " nvidia,tegra234-dsi"

nvidia,active-panel:

Description: - Contains the active panels under DSI

Customizable: No

Optional: No

Value: " NULL"

status:

Description: Holds the status of NvDisplay DSI node.

Customizable: No

Optional: No

Value: “okay” or “disabled”

Frozen Frame Detection

In order to enable frozen frame detection, these are the properties required. It uses the regional CRC approach.

regional-crc {
head0 {
/* num regions */ num-regions = <8>;

/* Array specifying "num-regions" region details.
*	Each region has 4 entries in array:
*	x-coordinate, y-coordinate, width and height
*/
regions = <100 100 200 200
400 300 200 200
700 100 100 300
900 200 400 300
1400 100 400 300
200 600 400 200
700 600 200 300
1200 600 400 300>;

/*
*	Display driver will use this value to declare
*	Frozen frame if CRC value for any region is repeated
*	these many times.
*/
ff-detection-threshold = <4>;
};
};

regional-crc:

Used to specify if regional CRC functionality can be enabled. If this entry is removed then FF detection functionality is disabled. This node is optional and only required if we need to enable Frozen Frame Detection.

head0:

Specifies which head the regional CRC is enabled on, ex:head0, head1. Orin has only two valid node names - head0 and head1. Either node, or both can be present based on which head/stream the Frozen Frame detection is to be enabled for.

num-regions:

Description: Specifies how many regions in given view-port will be used for regional crc comparison.

Customizable: Yes

Optional: No

Value: 1-9

regions:

Description: Used to mention different areas (upto 9) within a viewport on display image. Each region is described with 4 values mentioning the top left and bottom right coordinates.

Customizable: Yes

Optional: No

Value: All values are separated by space and start with values corresponding to the first region upto max allowed regions as mentioned in “num-regions'' property. The position and size of each region can be specified by the user.

For example:
  • <100100 200 200

    400300 200 200

    700100 100 300

    900200 400 300

    1400100 400 300

    200600 400 200

    700600 200 300

    1200600 400 300>

ff-detection-threshold:

Description: Used to specify after how many frames the FF detection is considered to be true. If the CRC for any single region remains the same for this many frames, the display driver will treat this as an error since it indicates that at least one region of the frame is stuck.

Customizable: Yes

Optional: No

Value: Integer specifying the number of frames. For example: <4>

Drive Setmode

When driver setmode is enabled, display setup + modeset will happen during the resmgr init phase instead of deferring this to when the first display client comes up. So, enabling driver setmode can improve "power-on to first pixel visible on screen" latency. On QNX safety, driver setmode is enabled by default. On QNX Standard, driver setmode can be enabled using Device Tree. Driver setmode can be enabled only for the configuration which uses DP Serializer, on other configurations enabling it will fail to load the display driver.

display@13800000 { nvidia,driver-setmode;
};

nvidia,driver-setmode:

Description: Used to enable driver setmode.

Customizable: No

Optional: Yes

Value: N/A

Head to Window Assignment

Used to configure head to window assignment in the Device Tree. If an assignment is not specified in the DT, the driver assigns windows (2N) and (2N + 1) to HEAD N. In DT, specify the assignment using 64 bit mask, which is interpreted as:

Head-Bitmask Window-Number
BITMASK(0-7) 0
BITMASK(8-15) 1
BITMASK(16-23) 2
BITMASK(24-31) 3
BITMASK(32-39) 4
BITMASK(40-47) 5
BITMASK(48-55) 6
BITMASK(56-63) 7

The display driver fails to load if an invalid assignment is specified in the DT. The specified assignment must adhere to the conditions below:

  1. The specified window number must be supported by hardware.
  2. The specified head number must be supported by hardware.
  3. The same window must not be assigned simultaneously for multiple heads.
  4. At least one window must be assigned to at least one head (that is, the specified window-head mask should not be 0).

The display driver culls the head with no windows assigned, and all the heads above it. For example, if hardware supports three heads and the user uses the assignment mask to assign valid windows to head-0 and head-2 but no windows to head-1, then head-1 and head-2 is culled.

display@13800000 {
nvidia,window-head-mask = <0x00000000 0x02010101>;
};

nvidia,window-head-mask:

Description: Used to specify the 64-bit window head assignment mask.

Customizable: Yes

Optional: Yes

Value: If no value is specified, a default head<->window assignment is used. If not, any value which fits the criteria mentioned above will work.

Static IMP

Starting from 6.0.5.0, QNX customers should enable static IMP. For enabling static IMP, we need to program certain IMP settings in BCT and Device Tree files. Generated using a host side tool called "laptsa-imp", we are able to generate this DT fragment.

static-imp-data {
/* Window and cursor pool config */
window-pool-config = <0x227 0x227 0x227 0x227>; cursor-pool-config = <0x1f 0x1f>;

/* Window and cursor drain meter config */
window-drain-meter-config = <0x20 0x20 0x20 0x20>; cursor-drain-meter-config = <0x3 0x3>;

/* Window and cursor fetch meter config */ window-fetch-meter-config = <0xf 0xf 0xf 0xf>; cursor-fetch-meter-config = <0x2 0x2>;

/* Delay before a START_FETCH command is sent to IsoHub */ start-fetch-delay-us = <0x1a8 0x1a8>;

/* Elv start value */ elv-start = <0x4 0x4>;

/* Clock Frequencies */ hub-clock-khz = <82300>;
disp-clock-khz = <311862>;
};
};

window-pool-config

Description: Specifies the window pool config.

Customizable: Yes

Optional: No

Value: Ex: <0x227 0x227 0x227 0x227>

cursor-pool-config

Description: Specifies the cursor pool config.

Customizable: Yes

Optional: No

Value: Ex: <0x1f 0x1f>

window-drain-meter-config

Description: Specifies the window drain meter config.

Customizable: Yes

Optional: No

Value: For example: <0x20 0x20 0x20 0x20>

cursor-drain-meter-config

Description: Specifies the cursor drain meter config.

Customizable: Yes

Optional: No

Value: For example: <0x3 0x3>

window-fetch-meter-config

Description: Specifies the window fetch meter config.

Customizable: Yes

Optional: No

Value: For example: <0xf 0xf 0xf 0xf>

cursor-fetch-meter-config

Description: Specifies the cursor fetch meter config.

Customizable: Yes

Optional: No

Value: For example: <0x2 0x2>

start-fetch-delay-us:

Description: Specifies the delay before a START_FETCH command is sent to IsoHub.

Customizable: Yes

Optional: No

Value: For example: <0x1a8 0x1a8>

elv-start:

Description: Specifies the Elv start value.

Customizable: Yes

Optional: No

Value: For example: <0x4 0x4>

hub-clock-khz:

Description: Specifies the IsoHub clock frequency in KHz.

Customizable: Yes

Optional: No

Value: For example: <82300>

disp-clock-khz:

Description: Specifies the display clock frequency in KHz.

Customizable: Yes

Optional: No

Value: For example: <311862>

Serializer

Configuring the Serializer Driver:

To use the NVIDIA reference Maxim serializer driver, there are various ways to configure the driver by Device Tree. An example Device Tree fragment is shown below that configures the Maxim serializer chip in MST mode:

maxim_ser: max_gmsl_dp_ser@40 { compatible = "maxim,max_gmsl_dp_ser"; reg = <0x40>;
status = "okay";
max_gmsl_dp_ser-pwrdn = <&tegra_main_gpio TEGRA234_MAIN_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
ser-errb = <&tegra_main_gpio TEGRA234_MAIN_GPIO(G, 7) 0>; dprx-link-rate = <0x1e>;
dprx-lane-count = <0x4>; enable-mst;
mst-payload-ids = <0x1 0x3 0x2 0x4>; gmsl-stream-ids = <0x0 0x1 0x2 0x3>; gmsl-link-select = <0x0 0x0 0x1 0x1>; enable-dp-fec;
enable-dsc = <1 0>;
enable-gmsl-fec = <1 0>;
};

compatible:

Description: `compatible` contains the unique string to identify the Maxim Serializer DT node.

Customizable: No

Optional: No

Value: "maxim,max_gmsl_dp_ser"

reg:

Description: - I2C address of the Maxim display serializer.

Customizable: No

Optional: No

Value: <0x40>

max_gmsl_dp_ser-pwrdn:

Description: - GPIO pin number of the PWRDN pin. This pin is used to power up the Maxim display serializer chip.

Customizable: No

Optional: No

Value: TEGRA234_MAIN_GPIO(G, 3) GPIO_ACTIVE_HIGH

gmsl-link-select:

Description: - This property is an array of four unsigned 8-bit values that determines the GMSL output link to enable for each video pipe X, Y, Z, and U.

Customizable: Yes

Optional: No

Value:The possible values for each pipe are:

  • 0x0 (Link A)
  • 0x1 (Link B)
  • 0x2 (Link A + B)

For example: <0x0 0x0 0x1 0x1>

dprx-link-rate:

Description: Configures the DP link rate of the serializer chip.

Customizable: Yes

Optional: Yes

Value: The default value is 0x1E (HBR3). The possible values are:

  • 0xA (HBR)
  • 0x14 (HBR2)
  • 0x1E (HBR3)

dprx-lane-count:

Description: Configures the DP lane count of the serializer chip.

Customizable: Yes

Optional: Yes

Value:The default value is 0x4. The possible values are:

  • 0x1
  • 0x2
  • 0x4

ser-errb:

Description: - Specifies the GPIO pin number of the ERRB pin. This pin is used for error and fault reporting by the serializer chip.

Customizable: No

Optional: Yes

Value: TEGRA234_MAIN_GPIO(G, 7) 0

enable-mst:

Description: - Used to enable MST modes.

Customizable: No

Optional: Yes

Value: N/A

mst-payload-ids:

Description: Used to represent MST payload IDs of pipe X, Y, Z, U. This property is mandatory if enable-mst property is mentioned in dt.

Customizable: Yes

Optional: Yes

Value: It is an array of four unsigned 8-bit values.

For example: <0x1 0x3 0x2 0x4>

gmsl-stream-ids:

Description: Used to represent GMSL stream IDs of pipe X, Y, Z, U. This property is mandatory if enable-mst property is mentioned in dt.

Customizable: Yes

Optional: Yes

Value: It is an array of four unsigned 8-bit values.

For example: <0x0 0x1 0x2 0x3>

enable-dp-fec:

Description: Used to enable FEC on DP link if serializer supports it.

Customizable: No

Optional: Yes

Value: N/A

enable-dsc:

Description: Used to enable DSC.

Customizable: Yes

Optional: Yes

Value: It is an array of two 32-bit values, where each value indicates whether DSC is enabled or not. The first entry corresponds to video pipe X, and the second entry corresponds to video pipe Y. DSC is only supported on pipe X currently.

For example: <1 0>

enable-gmsl-fec:

Description: - Used to enable FEC on the GMSL link.

Customizable: Yes

Optional: Yes

Value: It is an array of two 32-bit values, where each value indicates whether FEC is enabled on the GMSL link. The first entry corresponds to GMSL Link A, and the second entry corresponds to GMSL Link B.

For example: <1 0>

Configuring video timings:

For both SST and MST mode, the mode timings that are used for each stream must be configured in Device Tree. Only one mode timing can be specified at a time for each video stream. The timings that are exposed in the EDIDs of the serializer and the panels connected to the downstream deserializer are completely ignored.

An example Device Tree fragment is shown below. In this example, a standard 1920x1080 at 60 Hz timing is specified for the first video stream, and a 1280x720 at 60 Hz timing is specified for the second video stream:

display-timings {
display-connector-0 { dcb-index = <0>;

stream-0 {
timings-phandle = <&mode0>;
};

stream-1 {
timings-phandle = <&mode1>;
};
};
};
mode0: 1920-1080-60Hz {
clock-frequency-khz = <148500>;
hactive = <1920>;
vactive = <1080>;
hfront-porch = <88>;
hback-porch = <148>;
hsync-len = <44>;
vfront-porch = <4>;
vback-porch = <36>;
vsync-len = <5>;
rrx1k = <60000>;
pps-data = [
11 00 00 89 30 80 04 38
07 80 04 38 03 c0 03 c0
02 00 03 58 00 20 73 3e
00 0d 00 0f 00 1d 00 0e
18 00 10 f0 03 0c 20 00
06 0b 0b 33 0e 1c 2a 38
46 54 62 69 70 77 79 7b
7d 7e 01 02 01 00 09 40
09 be 19 fc 19 fa 19 f8
1a 38 1a 78 22 b6 2a b6
2a f6 2a f4 43 34 63 74
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 ];
};

mode1: 1280-720-60Hz {
clock-frequency-khz = <74250>;
hactive = <1280>;
vactive = <720>;
hfront-porch = <110>;
hback-porch = <220>;
hsync-len = <40>;
vfront-porch = <5>;
vback-porch = <20>;
vsync-len = <5>;
rrx1k = <60000>;
};

display-timings:

Used to describe which timings are used for each stream.

display-connector-0:

The node specifies the timing information for the first display connector. If there are multiple display connectors present on the board that require fixed timings, then a new "display-connector" node must be created for each connector.

dcb-index:

Description: Specifies the logical index X of the DCB -> Display Devices -> Display Device X entry in the display DCB blob that this connector entry applies to.

Customizable: Yes

Optional: No

Value: Has to be a valid logical index. If there is only one display connector on the board, then "dcb-index" defaults to 0.

stream-0:

The nodes specify the phandle of the mode timing node that applies to the given video stream. Each "display-connector" can only have up to two (2) "stream" nodes. Note that it is fine to specify two (2) "stream" nodes even if the display serializer operates in SST mode because only the first "stream" node is consumed by the display driver. The extra node is ignored.

timings-phandle:

Description: Specifies the phandle of the mode timing node.

Customizable: Yes

Optional: No

Value: N/A

mode0:

Each "mode" node contains the actual mode timing parameters that will be used for a given video stream.

clock-frequency-khz:

Description: Specifies the pixel clock frequency in KHz.

Customizable: Yes

Optional: No

Value: For example: <148500>

hactive:

Description: Horizontal active pixels.

Customizable: Yes

Optional: No

Value: For example: <1920>

vactive:

Description: Vertical active pixels.

Customizable: Yes

Optional: No

Value: For example: <1080>

hfront-porch:

Description: Horizontal front porch.

Customizable: Yes

Optional: No

Value: For example: <88>

hback-porch:

Description: Horizontal back porch.

Customizable: Yes

Optional: No

Value: For example: <148>

hsync-len:

Description: Horizontal sync width.

Customizable: Yes

Optional: No

Value: For example: <44>

vfront-porch:

Description: Vertical front porch.

Customizable: Yes

Optional: No

Value: For example: <4>

hback-porch:

Description: Horizontal back porch.

Customizable: Yes

Optional: No

Value: Ex: <36>

vsync-len:

Description: Vertical sync width.

Customizable: Yes

Optional: No

Value: Ex: <5>

rrx1k:

Description: Refresh rates in units of 0.001Hz.

Customizable: Yes

Optional: No

Value: For example: <60000>

pps-data:

Description: All 128B of the DSC PPS.

Customizable: Yes

Optional: Yes

Value: This property should be specified if DSC will be enabled for the given timing. For example:

[
11 00 00 89 30 80 04 38
07 80 04 38 03 c0 03 c0
02 00 03 58 00 20 73 3e
00 0d 00 0f 00 1d 00 0e
18 00 10 f0 03 0c 20 00
06 0b 0b 33 0e 1c 2a 38
46 54 62 69 70 77 79 7b
7d 7e 01 02 01 00 09 40
09 be 19 fc 19 fa 19 f8
1a 38 1a 78 22 b6 2a b6
2a f6 2a f4 43 34 63 74
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 ]

DCB Tool:

DCB tool is packaged in the following path:

$(SDK_TOOLS_DIR)/dcb_tool/dcb_tool

If you want to modify the DCB blob in DT, refer to the DCB documentation at:

$(SDK_TOOLS_DIR)/dcb_tool/readme.txt