PCIe Controller Device Tree

This section describes PCIe Resmgr interface specification.

PCIe_Resmgr_Device_Tree

compatible:

Description: Compatibility string name io-nv_pcie_manager.

Value: "nvidia,tegra234-pcie" for root port mode OR "nvidia,tegra234-pcie-ep" for end point mode.

Customizable: No

Optional: No

status:

Description: Enabled status of PCIe controller.

Value: "okay" or "disabled"

Customizable: No

Optional: No

num-lanes:

Description: Limits PCIe controller's link width to this value. This value should be same as controller's lane width in XBAR register.

Value: Valid values are 1/2/4/8

Customizable: Yes (As per XBAR setting for a platform.)

Optional: No

clocks:

Description: Contains the clock IDs for PCIe controller.

Value: Example for C0 Controller:

clocks = <&bpmp_clks TEGRA234_CLK_PEX0_CORE_0>,

<&bpmp_clks TEGRA234_CLK_PEX0_CORE_0_M>;

Customizable: No

Optional: No

resets:

Description: Contains the reset IDs for PCIe controller.

Value: Example for C0 Controller:

resets = <&bpmp_resets TEGRA194_RESET_PEX0_CORE_0_APB>,

<&bpmp_resets TEGRA194_RESET_PEX0_CORE_0>;

Customizable: No

Optional: No

reg:

Description: A list of physical base address and length pairs for each set of below registers

  • appl: Controller's application logic registers
  • config: PCIe config space
  • atu_dma: iATU and DMA registers. This is where the iATU (internal Address Translation Unit) and DMA registers of the PCIe core are made available for SW access.

    Above 3 are common for Both End Point and Root Port mode. Below 2 are applicable for Root port mode only:

    • addr_space_32: 32-bit aperture address range
    • addr_space_64: 64-bit aperture address range Below is applicable for End point mode only:
    • addr_space: End point aperture address space.

Value: Example for C0 Controller:

reg = <0x00 0x14100000 0x0 0x00020000 
0x00 0x31F80000 0x0 0x00040000
0x00 0x31FC0000 0x0 0x00040000
0x00 0x30000000 0x0 0x01F80000
0x20 0x80000000 0x0 0x40000000>;

Customizable: No

Optional: No

nvidia,cap-pl16g-cap-off:

Description:16.0 GT/s Capabilities Register. For a description of this standard PCIe register see the PCI Express Base Specification 4.0.

Value: Example for C0 Controller: nvidia,cap-pl16g-cap-off = <0x188>;

Customizable: No

Optional: No

nvidia,cfg-link-cap-l1sub:

Description: DBI register offset for ASPM L1 substate capabilities.

Value: Example for C0 Controller: nvidia,cfg-link-cap-l1sub = <0x1c4>;

Customizable: No

Optional: No

nvidia,enable-srns:

Description: This boolean property needs to be present if the platform has SRNS (Separate Reference clocks with No Spread-spectrum clocking) configuration implemented.

Customizable: Yes (As per platform configuration explained above).

Optional: Yes

phys:

Description: contain a phandle to P2U controller. This depends on platform configuration of phy lane assignment for each controller.

Value: Example for pcie@14100000 PCIe controller on P3710 platform phys = <&p2u_hsio_3>;

Customizable: Yes (As per platform assignment of the uphy lanes).

Optional: No

dma-coherent:

Description: boolean flag which indicates whether PCIe is DMA coherent or not.

Customizable: No

Optional: No

iommus:

Description: A list of phandle and IOMMU specifier pairs that describe the IOMMU master interfaces of the device. One entry in the list describes one master interface of the device.

Value: Example for C1 Controller - <&smmu_niso1 TEGRA_SID_NISO1_PCIE1>;

Customizable: No

Optional: No

memory-phandles:

Description: This property is used to find phandle of the node where typed memory name and memory mapping is d efined. This is used by EP client drivers to initialize descriptors and buffers in this memory range. Also, this is used by SMMU driver to create SMMU mappings.

Value: Example for C1 Controller

< &{/smmu-static-mapping/pcie1_smmu_static_mapping} >;
pcie1_smmu_static_mapping { mem-type = "TYPED_MEM"; mem-name = "pcie1Memory"; mem = <0x1 0x20000000 0x0 0x2000 0000>; };
Customizable: Yes, only applicable when End Point Driver needs Static SMMU mapping Optional: Yes, only applicable when End Point Driver needs Static SMMU mapping.

Customizable: Yes, only applicable when End Point Driver needs Static SMMU mapping Optional: Yes, only applicable when End Point Driver needs Static SMMU mapping.

Example:

pcie@14100000 {
compatible = "nvidia,tegra234-pcie"; reg = <0x00 0x14100000 0x0 0x00020000
0x00 0x31F80000 0x0 0x00040000
0x00 0x31FC0000 0x0 0x00040000
0x00 0x30000000 0x0 0x01F80000
0x20 0x80000000 0x0 0x40000000>;
status = "disabled"; num-lanes = <1>;
clocks = <&bpmp_clks TEGRA194_CLK_PEX0_CORE_1>,
<&bpmp_clks TEGRA194_CLK_PEX0_CORE_1_M>; resets = <&bpmp_resets TEGRA194_RESET_PEX0_CORE_1_APB>,
<&bpmp_resets TEGRA194_RESET_PEX0_CORE_1>; nvidia,cfg-link-cap-l1sub = <0x194>;
nvidia,cap-pl16g-cap-off = <0x178>; phys = <&p2u_hsio_3>;
...
};

P2U Controller Register

reg:

Description: Should be the physical address space and length of respective each P2U instance.

Value: Example for hsio_p2u p2u@03e10000 controller reg = <0x0 0x03e10000 0x0 0x00010000>;

Customizable: No

Optional: No

nvidia,skip-sz-protect-en:

Description: This is a boolean property and needs to be present if the platform is using SRNS clocking configuration and the number of retimers present between root port and endpoint are two.

It is applicable only for the two retimers case and not for the single retimer case.

Customizable: Yes (As per platform configuration mentioned in description).

Optional: No

Example:

p2u_hsio_0: phy@3e10000 {
reg = <0x03e10000 0x10000>;
nvidia,kip-sz-protect-en;
};