drive-os-linux-sdk/api_reference/nvethernetrm__export_8h_source.html

/*

 * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING

 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER

 * DEALINGS IN THE SOFTWARE.

 */


#ifndef INCLUDED_NVETHERNETRM_EXPORT_H

#define INCLUDED_NVETHERNETRM_EXPORT_H


#include <nvethernet_type.h>


#define OSI_GCL_SIZE_256        256U

#define OSI_MAX_TC_NUM          8U

/* Ethernet Address length */

#define OSI_ETH_ALEN            6U


/* Match data defines */

#define OSI_FRP_MATCH_DATA_MAX      12U


#define OSI_MTL_QUEUE_AVB   0x1U

#define OSI_MTL_QUEUE_ENABLE    0x2U

#define OSI_MTL_QUEUE_MODEMAX   0x3U


#define OSI_MTL_TXQ_AVALG_CBS   1U

#define OSI_MTL_TXQ_AVALG_SP    0U


#pragma pack(push, 1)


struct osi_core_frp_cmd {

    nveu32_t cmd;

    nve32_t frp_id;

    nveu8_t match_type;

    nveu8_t match[OSI_FRP_MATCH_DATA_MAX];

    nveu8_t match_length;

    nveu8_t offset;

    nveu8_t filter_mode;

    nve32_t next_frp_id;

    nveu32_t dma_sel;

};


struct  osi_core_avb_algorithm {

    nveu32_t qindex;

    nveu32_t algo;

    nveu32_t credit_control;

    nveu32_t idle_slope;

    nveu32_t send_slope;

    nveu32_t hi_credit;

    nveu32_t low_credit;

    nveu32_t oper_mode;

    nveu32_t tcindex;

};


struct osi_est_config {

    nveu32_t en_dis;

    nveu32_t btr[2];

    nveu32_t btr_offset[2];

    nveu32_t ctr[2];

    nveu32_t ter;

    nveu32_t llr;

    nveu32_t gcl[OSI_GCL_SIZE_256];

};


struct osi_fpe_config {

    nveu32_t tx_queue_preemption_enable;

    nveu32_t rq;

};


struct osi_tsn_stats {

    nveu64_t const_gate_ctr_err;

    nveu64_t head_of_line_blk_sch;

    nveu64_t hlbs_q[OSI_MAX_TC_NUM];

    nveu64_t head_of_line_blk_frm;

    nveu64_t hlbf_q[OSI_MAX_TC_NUM];

    nveu64_t base_time_reg_err;

    nveu64_t sw_own_list_complete;

};


struct osi_mmc_counters {

    nveu64_t mmc_tx_octetcount_gb;

    nveu64_t mmc_tx_octetcount_gb_h;

    nveu64_t mmc_tx_framecount_gb;

    nveu64_t mmc_tx_framecount_gb_h;

    nveu64_t mmc_tx_broadcastframe_g;

    nveu64_t mmc_tx_broadcastframe_g_h;

    nveu64_t mmc_tx_multicastframe_g;

    nveu64_t mmc_tx_multicastframe_g_h;

    nveu64_t mmc_tx_64_octets_gb;

    nveu64_t mmc_tx_64_octets_gb_h;

    nveu64_t mmc_tx_65_to_127_octets_gb;

    nveu64_t mmc_tx_65_to_127_octets_gb_h;

    nveu64_t mmc_tx_128_to_255_octets_gb;

    nveu64_t mmc_tx_128_to_255_octets_gb_h;

    nveu64_t mmc_tx_256_to_511_octets_gb;

    nveu64_t mmc_tx_256_to_511_octets_gb_h;

    nveu64_t mmc_tx_512_to_1023_octets_gb;

    nveu64_t mmc_tx_512_to_1023_octets_gb_h;

    nveu64_t mmc_tx_1024_to_max_octets_gb;

    nveu64_t mmc_tx_1024_to_max_octets_gb_h;

    nveu64_t mmc_tx_unicast_gb;

    nveu64_t mmc_tx_unicast_gb_h;

    nveu64_t mmc_tx_multicast_gb;

    nveu64_t mmc_tx_multicast_gb_h;

    nveu64_t mmc_tx_broadcast_gb;

    nveu64_t mmc_tx_broadcast_gb_h;

    nveu64_t mmc_tx_underflow_error;

    nveu64_t mmc_tx_underflow_error_h;

    nveu64_t mmc_tx_singlecol_g;

    nveu64_t mmc_tx_multicol_g;

    nveu64_t mmc_tx_deferred;

    nveu64_t mmc_tx_latecol;

    nveu64_t mmc_tx_exesscol;

    nveu64_t mmc_tx_carrier_error;

    nveu64_t mmc_tx_octetcount_g;

    nveu64_t mmc_tx_octetcount_g_h;

    nveu64_t mmc_tx_framecount_g;

    nveu64_t mmc_tx_framecount_g_h;

    nveu64_t mmc_tx_excessdef;

    nveu64_t mmc_tx_pause_frame;

    nveu64_t mmc_tx_pause_frame_h;

    nveu64_t mmc_tx_vlan_frame_g;

    nveu64_t mmc_tx_vlan_frame_g_h;

    nveu64_t mmc_tx_osize_frame_g;

    nveu64_t mmc_rx_framecount_gb;

    nveu64_t mmc_rx_framecount_gb_h;

    nveu64_t mmc_rx_octetcount_gb;

    nveu64_t mmc_rx_octetcount_gb_h;

    nveu64_t mmc_rx_octetcount_g;

    nveu64_t mmc_rx_octetcount_g_h;

    nveu64_t mmc_rx_broadcastframe_g;

    nveu64_t mmc_rx_broadcastframe_g_h;

    nveu64_t mmc_rx_multicastframe_g;

    nveu64_t mmc_rx_multicastframe_g_h;

    nveu64_t mmc_rx_crc_error;

    nveu64_t mmc_rx_crc_error_h;

    nveu64_t mmc_rx_align_error;

    nveu64_t mmc_rx_runt_error;

    nveu64_t mmc_rx_jabber_error;

    nveu64_t mmc_rx_undersize_g;

    nveu64_t mmc_rx_oversize_g;

    nveu64_t mmc_rx_64_octets_gb;

    nveu64_t mmc_rx_64_octets_gb_h;

    nveu64_t mmc_rx_65_to_127_octets_gb;

    nveu64_t mmc_rx_65_to_127_octets_gb_h;

    nveu64_t mmc_rx_128_to_255_octets_gb;

    nveu64_t mmc_rx_128_to_255_octets_gb_h;

    nveu64_t mmc_rx_256_to_511_octets_gb;

    nveu64_t mmc_rx_256_to_511_octets_gb_h;

    nveu64_t mmc_rx_512_to_1023_octets_gb;

    nveu64_t mmc_rx_512_to_1023_octets_gb_h;

    nveu64_t mmc_rx_1024_to_max_octets_gb;

    nveu64_t mmc_rx_1024_to_max_octets_gb_h;

    nveu64_t mmc_rx_unicast_g;

    nveu64_t mmc_rx_unicast_g_h;

    nveu64_t mmc_rx_length_error;

    nveu64_t mmc_rx_length_error_h;

    nveu64_t mmc_rx_outofrangetype;

    nveu64_t mmc_rx_outofrangetype_h;

    nveu64_t mmc_rx_pause_frames;

    nveu64_t mmc_rx_pause_frames_h;

    nveu64_t mmc_rx_fifo_overflow;

    nveu64_t mmc_rx_fifo_overflow_h;

    nveu64_t mmc_rx_vlan_frames_gb;

    nveu64_t mmc_rx_vlan_frames_gb_h;

    nveu64_t mmc_rx_watchdog_error;

    nveu64_t mmc_rx_receive_error;

    nveu64_t mmc_rx_ctrl_frames_g;

    nveu64_t mmc_tx_lpi_usec_cntr;

    nveu64_t mmc_tx_lpi_tran_cntr;

    nveu64_t mmc_rx_lpi_usec_cntr;

    nveu64_t mmc_rx_lpi_tran_cntr;

    nveu64_t mmc_rx_ipv4_gd;

    nveu64_t mmc_rx_ipv4_gd_h;

    nveu64_t mmc_rx_ipv4_hderr;

    nveu64_t mmc_rx_ipv4_hderr_h;

    nveu64_t mmc_rx_ipv4_nopay;

    nveu64_t mmc_rx_ipv4_nopay_h;

    nveu64_t mmc_rx_ipv4_frag;

    nveu64_t mmc_rx_ipv4_frag_h;

    nveu64_t mmc_rx_ipv4_udsbl;

    nveu64_t mmc_rx_ipv4_udsbl_h;

    nveu64_t mmc_rx_ipv6_gd_octets;

    nveu64_t mmc_rx_ipv6_gd_octets_h;

    nveu64_t mmc_rx_ipv6_hderr_octets;

    nveu64_t mmc_rx_ipv6_hderr_octets_h;

    nveu64_t mmc_rx_ipv6_nopay_octets;

    nveu64_t mmc_rx_ipv6_nopay_octets_h;

    /* Protocols */

    nveu64_t mmc_rx_udp_gd;

    nveu64_t mmc_rx_udp_gd_h;

    nveu64_t mmc_rx_udp_err;

    nveu64_t mmc_rx_udp_err_h;

    nveu64_t mmc_rx_tcp_gd;

    nveu64_t mmc_rx_tcp_gd_h;

    nveu64_t mmc_rx_tcp_err;

    nveu64_t mmc_rx_tcp_err_h;

    nveu64_t mmc_rx_icmp_gd;

    nveu64_t mmc_rx_icmp_gd_h;

    nveu64_t mmc_rx_icmp_err;

    nveu64_t mmc_rx_icmp_err_h;

    nveu64_t mmc_rx_ipv4_gd_octets;

    nveu64_t mmc_rx_ipv4_gd_octets_h;

    nveu64_t mmc_rx_ipv4_hderr_octets;

    nveu64_t mmc_rx_ipv4_hderr_octets_h;

    nveu64_t mmc_rx_ipv4_nopay_octets;

    nveu64_t mmc_rx_ipv4_nopay_octets_h;

    nveu64_t mmc_rx_ipv4_frag_octets;

    nveu64_t mmc_rx_ipv4_frag_octets_h;

    nveu64_t mmc_rx_ipv4_udsbl_octets;

    nveu64_t mmc_rx_ipv4_udsbl_octets_h;

    nveu64_t mmc_rx_ipv6_gd;

    nveu64_t mmc_rx_ipv6_gd_h;

    nveu64_t mmc_rx_ipv6_hderr;

    nveu64_t mmc_rx_ipv6_hderr_h;

    nveu64_t mmc_rx_ipv6_nopay;

    nveu64_t mmc_rx_ipv6_nopay_h;

    /* Protocols */

    nveu64_t mmc_rx_udp_gd_octets;

    nveu64_t mmc_rx_udp_gd_octets_h;

    nveu64_t mmc_rx_udp_err_octets;

    nveu64_t mmc_rx_udp_err_octets_h;

    nveu64_t mmc_rx_tcp_gd_octets;

    nveu64_t mmc_rx_tcp_gd_octets_h;

    nveu64_t mmc_rx_tcp_err_octets;

    nveu64_t mmc_rx_tcp_err_octets_h;

    nveu64_t mmc_rx_icmp_gd_octets;

    nveu64_t mmc_rx_icmp_gd_octets_h;

    nveu64_t mmc_rx_icmp_err_octets;

    nveu64_t mmc_rx_icmp_err_octets_h;

    nveu64_t mmc_tx_fpe_frag_cnt;

    nveu64_t mmc_tx_fpe_hold_req_cnt;

    nveu64_t mmc_rx_packet_reass_err_cnt;

    nveu64_t mmc_rx_packet_smd_err_cnt;

    nveu64_t mmc_rx_packet_asm_ok_cnt;

    nveu64_t mmc_rx_fpe_fragment_cnt;

};


#pragma pack(pop)

#endif /* INCLUDED_NVETHERNETRM_EXPORT_H */