The Tegra 2 Technical Reference Manual ("TRM") is a technical document of over 1,300 pages targeted at those working on open source or other low level software projects that use or target the Tegra 2 processor. The TRM focuses on the logical organization and control of Tegra 2 Series devices. It provides information for those modules that interface to external devices, or those that control fundamental chip operations. The modules detailed in this document provide an overview, any necessary programming guidelines, and a register listing for that module. Internal functional units such as video and graphics hardware acceleration are controlled by NVIDIA provided software and not documented.

NVIDIA provides access to the Tegra 2 TRM to registered developers only. To become a registered developer, please sign up for our GameWorks Registered Developer Program.

If you are already a Registered Developer you can download the TRM from our Download Center.

Table of Contents

  1. Introduction
    1. Block Diagram
    2. Memory Controller and Internal Bus Architecture
    3. Reading Register Tables
    4. Glossary
  2. Address and Interrupt Map
    1. System Memory Map
    2. Access Restrictions
    3. Interrupt Mapping
    4. APB DMA Interrupts
  3. Interrupt Controller
    1. Functionality
    2. Interrupt Registers
  4. Arbitration Semaphores
    1. Overview
    2. Semaphore Registers
  5. Clock and Reset Controller
    1. Hardware Features
    2. Clocking Block Diagrams
    3. Software Features and Programming Model
    4. Clock and Reset Controller Registers
  6. Real-Time Clock
    1. Functional Description
    2. RTC Registers
  7. Timers
    1. Functionality
    2. Watchdog Timer Programming Guide
    3. Timer Registers
    4. Timer USEC CFG
    5. CNTR_1US Register
  8. Pin Muxing
    1. Pad Groups
    2. Programming Interface
    3. Pin Mux Use Case Configuration Examples
    4. Dynamic Pin Muxing
  9. Power
    1. Power Management Controller
    2. Dynamic Voltage Controller
  10. AHB
    1. AHB Bus
    2. AHB Bus Arbiter
    3. AHB “Gizmo”
    4. AHB Memory Controller Slave
    5. AHB DMA Controller
  11. APB
    1. APB Miscellaneous Registers
    2. APB DMA Controller
  12. CPU
    1. CPU Timers
  13. Flow Controller
    1. Flow Controller Registers
  14. Level 2 Cache Controller
  15. Memory Controller
    1. Usage Modes
    2. Programming Sequence
    3. Performance Configuration Registers
    4. Memory Controller Registers
  16. NAND Flash Controller
    1. Features
    2. Functional Description
    3. Programming Guidelines
    4. NAND Registers
  17. GMI Controller
    1. Functional Description
    2. Programming Guidelines
    3. GMI Registers
  18. GPIO Controller
    1. Functionality
    2. GPIO Registers
  19. Keyboard Controller
    1. Functionality
    2. Micro-Architecture
    3. KBC Registers
  20. PWFM Controller
    1. Functionality
    2. PWFM Registers
  21. I2C Controller
    1. Functionality
    2. Interfaces
    3. Programming Guidelines
    4. Programming Guidelines for Packet Based Interface
    5. I2C Registers
  22. UART and VFIR Controller
    1. Hardware Features
    2. Hardware Signaling
    3. Functionality
    4. UART Programming Guidelines
    5. VFIR Programming Guidelines
    6. UART Registers
    7. VFIR Registers
  23. SPI Controller
    1. SLINK: SPI Peripheral Interface
    2. SPI Serial Flash Controller
  24. One Wire Battery Controller
    1. Functionality
    2. Programming Guidelines
    3. OWR Registers
  25. SD/MMC Controller
    1. Operation
    2. Block Diagram
    3. Programming Guidelines
    4. SDMMC Registers
    5. Vendor Specific SDMMC Registers
  26. USB Complex
    1. USB Controllers and Interfaces
    2. Controller
    3. USB Programming Guidelines
    4. UTMIP Programming Guidelines
    5. USB Registers
  27. Audio Subsystem
    1. Digital Audio Switch
    2. I2S Controller
    3. S/PDIF Controller
  28. Camera Serial Interface (MIPI-CSI)
    1. Use Cases
    2. Input Data Format
    3. CSI Packet Structure
    4. CSI Implementation
    5. Performance Limitations
    6. Error Resilience
    7. Other Architectural Constraints
    8. CSI Datapath Module
    9. Software Requirements
    10. DPHY Modes of Operation
    11. MIPI-CSI Registers
  29. Display Controller
    1. Hardware Interface
    2. Functionality
    3. VESA Timings
    4. Television Timings
    5. Programming
    6. Display Controller Register Definition
    7. Display CMD Registers
    8. Display COM Registers
    9. Display DISP Registers
    10. Window A (WINC_A) Registers
    11. WINBUF_A Registers
    12. Window B (WINC_B) Registers
    13. WINBUF_B Registers
    14. Window C (WIN_C) Registers
    15. WINBUF_C Registers
  30. Display Serial Interface (MIPI-DSI)
    1. Clocking
    2. Operating Modes
    3. Display Controller Interface
    4. Host Interface
    5. FIFO Buffers
    6. Programming Guidelines
    7. MIPI-DSI Registers
  31. PCIe (Tegra 250 Only)
    1. Supported Configurations and Limitations
    2. Registers