GTC Silicon Valley-2019: Tensor Core Programmability and Profiling for AI and HPC Applications
GTC Silicon Valley-2019 ID:S9542:Tensor Core Programmability and Profiling for AI and HPC Applications
Max Katz(NVIDIA),Griffin Lacey(NVIDIA)
Tensor Cores, introduced with Volta GPU architecture, achieve up to 125 TFlops throughput by mixing half- and single-precision floating point operations. We'll show how to take advantage of Tensor Cores for applications in deep learning and HPC. We will discuss how to use mixed precision to decrease memory use during deep learning training and deployment, a technique that allows for larger model sizes. We will also demonstrate programming matrix-multiply-and-accumulate on Tensor Cores for HPC applications. Using NVIDIA Nsight, we will profile an application to understand use of Tensor Cores.