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Jetson Sensor Processing Engine (SPE) Developer Guider32.2 Release |
This section explains how to use the CAN application on NVIDIA® Jetson™ TX 2 and AGX.
There are two CAN controllers, which run in Always On (AON) mode. As such, the APIs that interface with those controllers are called AON CAN controller driver APIs. This application demonstrates how to use them.
To control compilation of the CAN application, use the ENABLE_CAN_APP
flag in the soc/*/target_specific.mk
file.
Before you can to successfully execute the application, you must obtain two CAN transceivers. The transceivers must be 3.3V I/O compatible, similar to the ones at:
https://www.amazon.com/SN65HVD230-CAN-Board-Communication-Development/dp/B00KM6XMXO
By default, the CAN AON controller driver sets the bit rate at 500-kilobits per second and the data bit rate at 2-megabits per second. For more information, see the mttcan_controller_init
function in the tegra-can.c
driver source file.
The application uses both AON CAN controllers. It also connects the CAN 0 bus to CAN 1, using the above mentioned CAN transceivers, where:
The application prints the message details received at CAN 1 bus. It also prints the transmit element, which includes information about the transmitted message. The transmit element is also created when there is a bus state change. Below is the sample output that is printed on successful transmission.
Transmited message from CAN 0 Transmission complete event Transmit event element information: Message ID: 0xa5, Event Type: Tx event, CAN Frame: <frame details> Message received at CAN 1 Message ID: 0xa5, Message data length: 2 Message Data: 0xaa 0x55
Ensure the CAN is disabled in the kernel device tree tegra186-quill-p3310-1000-c03-00-base.dts
as shown below:
CAN 0 and 1 controller TX and RX are brought out to 30 pin header J26 as below:
Additional 3.3V and GND connections are available at 40 pin header J21 as below:
Ensure the CAN is disabled in the kernel device tree tegra194-p2888-0001-p2822-0000-common.dtsi
as shown below:
Modify SCR setting in tegra194-mb1-bct-scr-cbb-mini.cfg as follows:
Modify pinmux setting in tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg as follows:
CAN 0 and 1 controller TX and RX are brought out to 40 pin header J30 as below: