Developer Newsletter: Issue #5

Coding Tip

When rendering using the hardware transform-and-lighting (TnL) pipeline or vertex-shaders, the GPU intermittently caches transformed and lit vertices. Storing these post-transform and lighting (post-TnL) vertices avoids recomputing the same values whenever a vertex is shared between multiple triangles and thus saves time. The post-TnL cache increases rendering performance by up to 2x.

Because the post-TnL cache is limited in size, taking maximum advantage of it requires rearranging triangle rendering-order. The easiest way to rearrange triangle-order for the post-TnL cache is to use the NVTriStrip library (.LIBs and source are available for free: here).

If you are interested in exploring the performance characteristics of the post-TnL cache yourself, here are the details: The post-TnL cache is a strict First-In-First-Out buffer, and varies in size from effectively 10 (actual 16) vertices on GeForce 256, GeForce 2, and GeForce 4 MX chipsets to effectively 18 (actual 24) on GeForce 3 and GeForce 4 Ti chipsets. Non-indexed draw-calls cannot take advantage of the cache, as it is then impossible for the GPU to know which vertices are shared.

The following example explores how these restrictions translate into optimally rendering a 100x100 vertex mesh. The mesh needs to be submitted in a single draw-call to optimize batch-size. The draw-call must be with an indexed primitive-type (see above), either strips or lists -- the performance difference between strips and lists is negligible when taking advantage of the post-TnL cache. For illustration purposes, our example uses strips.

Rendering the mesh as 99 strips running along each row of triangles and stitching them together into a single strip with degenerate triangles only marginally takes advantage of the post-TnL cache. Only two vertices in each triangle hit the post-TnL cache (i.e., one vertex is transformed and lit per triangle).

Let's limit the length of each row-strip to at most 2*16 = 32 triangles. The mesh thus separates into ceil(99/16) = 7 columns of strips, each no longer than 32 triangles. Rendering all row-strips in column 0 first, from top to bottom and connected via degenerate triangles, allows an 18 entry post-TnL cache to store not only the last two vertices for each triangle but also the whole top row of vertices for each row-strip. Thus, only 1 vertex for every 2 triangles needs to be computed. For the vertices to be in just the right order such that the top row of vertices is in the post-TnL cache, the top-row of vertices of each column should be sent as a list of degenerate triangles.